/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * cortex_m7 version: 1.0
 * cortex_m7 authors: Aidan MacDonald
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __ARM_CORTEX_M_CACHE_H__
#define __ARM_CORTEX_M_CACHE_H__

#include "macro.h"

#define REG_CACHE_ICIALLU   cm_reg(CACHE_ICIALLU)
#define CMA_CACHE_ICIALLU   (0xe000e000 + 0xf50)
#define CMT_CACHE_ICIALLU   CMIO_32_RW
#define CMN_CACHE_ICIALLU   CACHE_ICIALLU

#define REG_CACHE_ICIMVAU   cm_reg(CACHE_ICIMVAU)
#define CMA_CACHE_ICIMVAU   (0xe000e000 + 0xf58)
#define CMT_CACHE_ICIMVAU   CMIO_32_RW
#define CMN_CACHE_ICIMVAU   CACHE_ICIMVAU

#define REG_CACHE_DCIMVAC   cm_reg(CACHE_DCIMVAC)
#define CMA_CACHE_DCIMVAC   (0xe000e000 + 0xf5c)
#define CMT_CACHE_DCIMVAC   CMIO_32_RW
#define CMN_CACHE_DCIMVAC   CACHE_DCIMVAC

#define REG_CACHE_DCISW cm_reg(CACHE_DCISW)
#define CMA_CACHE_DCISW (0xe000e000 + 0xf60)
#define CMT_CACHE_DCISW CMIO_32_RW
#define CMN_CACHE_DCISW CACHE_DCISW

#define REG_CACHE_DCCMVAU   cm_reg(CACHE_DCCMVAU)
#define CMA_CACHE_DCCMVAU   (0xe000e000 + 0xf64)
#define CMT_CACHE_DCCMVAU   CMIO_32_RW
#define CMN_CACHE_DCCMVAU   CACHE_DCCMVAU

#define REG_CACHE_DCCMVAC   cm_reg(CACHE_DCCMVAC)
#define CMA_CACHE_DCCMVAC   (0xe000e000 + 0xf68)
#define CMT_CACHE_DCCMVAC   CMIO_32_RW
#define CMN_CACHE_DCCMVAC   CACHE_DCCMVAC

#define REG_CACHE_DCCSW cm_reg(CACHE_DCCSW)
#define CMA_CACHE_DCCSW (0xe000e000 + 0xf6c)
#define CMT_CACHE_DCCSW CMIO_32_RW
#define CMN_CACHE_DCCSW CACHE_DCCSW

#define REG_CACHE_DCCIMVAC  cm_reg(CACHE_DCCIMVAC)
#define CMA_CACHE_DCCIMVAC  (0xe000e000 + 0xf70)
#define CMT_CACHE_DCCIMVAC  CMIO_32_RW
#define CMN_CACHE_DCCIMVAC  CACHE_DCCIMVAC

#define REG_CACHE_DCCISW    cm_reg(CACHE_DCCISW)
#define CMA_CACHE_DCCISW    (0xe000e000 + 0xf74)
#define CMT_CACHE_DCCISW    CMIO_32_RW
#define CMN_CACHE_DCCISW    CACHE_DCCISW

#endif /* __ARM_CORTEX_M_CACHE_H__*/