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ColdFire: DCR is a 16-bit register

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6604 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Linus Nielsen Feltzing 2005-06-08 07:37:32 +00:00
parent aa9c329dbe
commit cff83c78c7
3 changed files with 8 additions and 8 deletions
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4
firmware/crt0.S
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@ -190,8 +190,8 @@ irq_handler:
/* Set up the DRAM controller. The refresh is based on the 11.2896MHz
clock (5.6448MHz bus frequency). We haven't yet started the PLL */
move.l #0x80010000,%d0
move.l %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */
move.w #0x8001,%d0
move.w %d0,(0x100,%a0) /* DCR - Synchronous, 32 cycle refresh */
/* Note: we place the SDRAM on an 0x1000000 (16M) offset because
the 5249 BGA chip has a fault which disables the use of A24. The