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Sansa AMS: Various fixes/enhancements for clock frequencies

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Fix CGU_DBOP setting

Set PCLK to the exact frequency (62MHz, not the maximal frequency)

Use a better comment for CLK_DIV macro

Use preprocessor safety checks for clock divider sizes to avoid future mistakes (not for SD_IDENT frequency since that check is handled by mci_set_clock_divider)

Use maximal IDE frequency of 66MHz (like OF), not 90MHz like written in AS3525 datasheet. The IDE chip is somehow linked to internal storage, and a too high frequency could affect the storage driver.

Use the same DBOP frequency of 32MHz for all models (like OF, verified clip, fuze, e200v2 and m200v4), compromise between performance and battery life could be added in the future for each target
Performance increase on Sansa Fuze with DBOP freq. set to 64MHz: +12% fps for lcd_update, +1% fps for yuv

Thanks to daytona955 on the forums for his help

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20923 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2009-05-13 08:27:20 +00:00
parent 49ba646d57
commit adb978a44d
5 changed files with 25 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

41
firmware/target/arm/as3525/clock-target.h
View file

@ -21,6 +21,9 @@
#ifndef CLOCK_TARGET_H
#define CLOCK_TARGET_H
/* returns clock divider, given maximal target frequency and clock reference */
#define CLK_DIV(ref, target) ((ref + target - 1) / target)
/* PLL */
#define AS3525_PLLA_FREQ 248000000
@ -39,28 +42,26 @@
/* peripherals */
#define AS3525_PCLK_FREQ 65000000
#define AS3525_PCLK_FREQ 62000000
#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
#error PCLK frequency is too low : clock divider will not fit !
#endif
#define AS3525_IDE_FREQ 90000000
#define AS3525_IDE_FREQ 66000000
#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
#error IDE frequency is too low : clock divider will not fit !
#endif
#define AS3525_I2C_FREQ 400000
#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_I2C_FREQ)) >= (1<<16) /* 2*8 bits */
#error I2C frequency is too low : clock divider will not fit !
#endif
#define AS3525_DBOP_FREQ 32000000
#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
#error DBOP frequency is too low : clock divider will not fit !
#endif
#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
#define AS3525_I2C_FREQ 400000
/* LCD controller : varies on the models */
#if defined(SANSA_CLIP)
#define AS3525_DBOP_FREQ 6000000
#elif defined(SANSA_M200V4)
#define AS3525_DBOP_FREQ 8000000
#elif defined(SANSA_FUZE)
#define AS3525_DBOP_FREQ 8000000
#elif defined(SANSA_E200V2)
#define AS3525_DBOP_FREQ 8000000
#elif defined(SANSA_C200V2)
#define AS3525_DBOP_FREQ 8000000
#endif
/* macro for not giving a target clock > at the one provided */
#define CLK_DIV(ref, target) ((ref + target - 1) / target)
#endif /* CLOCK_TARGET_H */

2
firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c
View file

@ -98,7 +98,7 @@ static void lcd_delay(int x)
/* DBOP initialisation, do what OF does */
static void ams3525_dbop_init(void)
{
CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
DBOP_TIMPOL_01 = 0xe167e167;
DBOP_TIMPOL_23 = 0xe167006e;

2
firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c
View file

@ -70,7 +70,7 @@
/* DBOP initialisation, do what OF does */
static void ams3525_dbop_init(void)
{
CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
CGU_DBOP |= (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */
GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */

2
firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c
View file

@ -108,7 +108,7 @@ static void lcd_delay(int x)
/* DBOP initialisation, do what OF does */
static void ams3525_dbop_init(void)
{
CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
DBOP_TIMPOL_01 = 0xe167e167;
DBOP_TIMPOL_23 = 0xe167006e;

2
firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c
View file

@ -50,7 +50,7 @@ static bool lcd_busy = false;
static void as3525_dbop_init(void)
{
CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ);
CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1);
DBOP_TIMPOL_01 = 0xe167e167;
DBOP_TIMPOL_23 = 0xe167006e;