diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index a227f464ff..21fd4c65d2 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h @@ -21,6 +21,9 @@ #ifndef CLOCK_TARGET_H #define CLOCK_TARGET_H +/* returns clock divider, given maximal target frequency and clock reference */ +#define CLK_DIV(ref, target) ((ref + target - 1) / target) + /* PLL */ #define AS3525_PLLA_FREQ 248000000 @@ -39,28 +42,26 @@ /* peripherals */ -#define AS3525_PCLK_FREQ 65000000 +#define AS3525_PCLK_FREQ 62000000 +#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */ +#error PCLK frequency is too low : clock divider will not fit ! +#endif -#define AS3525_IDE_FREQ 90000000 +#define AS3525_IDE_FREQ 66000000 +#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */ +#error IDE frequency is too low : clock divider will not fit ! +#endif + +#define AS3525_I2C_FREQ 400000 +#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_I2C_FREQ)) >= (1<<16) /* 2*8 bits */ +#error I2C frequency is too low : clock divider will not fit ! +#endif + +#define AS3525_DBOP_FREQ 32000000 +#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */ +#error DBOP frequency is too low : clock divider will not fit ! +#endif #define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */ -#define AS3525_I2C_FREQ 400000 - -/* LCD controller : varies on the models */ -#if defined(SANSA_CLIP) -#define AS3525_DBOP_FREQ 6000000 -#elif defined(SANSA_M200V4) -#define AS3525_DBOP_FREQ 8000000 -#elif defined(SANSA_FUZE) -#define AS3525_DBOP_FREQ 8000000 -#elif defined(SANSA_E200V2) -#define AS3525_DBOP_FREQ 8000000 -#elif defined(SANSA_C200V2) -#define AS3525_DBOP_FREQ 8000000 -#endif - -/* macro for not giving a target clock > at the one provided */ -#define CLK_DIV(ref, target) ((ref + target - 1) / target) - #endif /* CLOCK_TARGET_H */ diff --git a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c index 88adcd9d96..0ffe0bdc8d 100644 --- a/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c +++ b/firmware/target/arm/as3525/sansa-c200v2/lcd-c200v2.c @@ -98,7 +98,7 @@ static void lcd_delay(int x) /* DBOP initialisation, do what OF does */ static void ams3525_dbop_init(void) { - CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_23 = 0xe167006e; diff --git a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c index 4669abdf7d..a88e5faa0a 100644 --- a/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c +++ b/firmware/target/arm/as3525/sansa-clip/lcd-ssd1303.c @@ -70,7 +70,7 @@ /* DBOP initialisation, do what OF does */ static void ams3525_dbop_init(void) { - CGU_DBOP |= (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP |= (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); GPIOB_AFSEL = 0x08; /* DBOP on pin 3 */ GPIOC_AFSEL = 0x0f; /* DBOP on pins 3:0 */ diff --git a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c index ef21893494..9e23dac340 100644 --- a/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c +++ b/firmware/target/arm/as3525/sansa-e200v2/lcd-e200v2.c @@ -108,7 +108,7 @@ static void lcd_delay(int x) /* DBOP initialisation, do what OF does */ static void ams3525_dbop_init(void) { - CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_23 = 0xe167006e; diff --git a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c index 141b890861..f0c85f53b4 100644 --- a/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c +++ b/firmware/target/arm/as3525/sansa-fuze/lcd-fuze.c @@ -50,7 +50,7 @@ static bool lcd_busy = false; static void as3525_dbop_init(void) { - CGU_DBOP = (1<<3) | CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ); + CGU_DBOP = (1<<3) | (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1); DBOP_TIMPOL_01 = 0xe167e167; DBOP_TIMPOL_23 = 0xe167006e;