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zen/zenxfi: fix incorrect dotclk polarity

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By default STMP3700 launches from negative edge for capture on positive edge.
If we leave DPL (bit 13 of reg 0x13) to 0, it will be captured on falling edge,
resulting in a potentially undefined behavior. Some make sure LCD captures on
rising edge. Alternatively we could change the dotclk polarity in VDCTRL0.

Change-Id: I4ceb2f5a9be88e07f0af9bf493b7881883320fda
This commit is contained in:
Amaury Pouly 2017-01-14 18:40:14 +01:00 • committed by Solomon Peachy
parent 4ad041e17a
commit ac6822debb
1 changed files with 1 additions and 1 deletions
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2
firmware/target/arm/imx233/creative-zen/lcd-zen.c
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@ -174,7 +174,7 @@ static void lcd_init_seq(void)
spi_write_reg(0x2, 0x300); spi_write_reg(0x2, 0x300);
/* NOTE by default stmp3700 has vsync/hsync active low and data launch /* NOTE by default stmp3700 has vsync/hsync active low and data launch
* at negative edge of dotclk, reflect this in the polarity settings */ * at negative edge of dotclk, reflect this in the polarity settings */
spi_write_reg(0x3, 0xd040);// polarity (OF uses 0xc040, seems incorrect) spi_write_reg(0x3, 0xf040);// OF uses 0xc040, but DS says bit 12 must be set
spi_write_reg(0x8, 0); // vsync back porch (0=3H) spi_write_reg(0x8, 0); // vsync back porch (0=3H)
spi_write_reg(0x9, 0); // hsync back porch (0=24clk) spi_write_reg(0x9, 0); // hsync back porch (0=24clk)
spi_write_reg(0x76, 0x2213); spi_write_reg(0x76, 0x2213);