From ac6822debb1c938e0c09abeaa6e9d5ee89253d5d Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Sat, 14 Jan 2017 18:40:14 +0100 Subject: [PATCH] zen/zenxfi: fix incorrect dotclk polarity By default STMP3700 launches from negative edge for capture on positive edge. If we leave DPL (bit 13 of reg 0x13) to 0, it will be captured on falling edge, resulting in a potentially undefined behavior. Some make sure LCD captures on rising edge. Alternatively we could change the dotclk polarity in VDCTRL0. Change-Id: I4ceb2f5a9be88e07f0af9bf493b7881883320fda --- firmware/target/arm/imx233/creative-zen/lcd-zen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/target/arm/imx233/creative-zen/lcd-zen.c b/firmware/target/arm/imx233/creative-zen/lcd-zen.c index 3d92954808..e8c1ef74de 100644 --- a/firmware/target/arm/imx233/creative-zen/lcd-zen.c +++ b/firmware/target/arm/imx233/creative-zen/lcd-zen.c @@ -174,7 +174,7 @@ static void lcd_init_seq(void) spi_write_reg(0x2, 0x300); /* NOTE by default stmp3700 has vsync/hsync active low and data launch * at negative edge of dotclk, reflect this in the polarity settings */ - spi_write_reg(0x3, 0xd040);// polarity (OF uses 0xc040, seems incorrect) + spi_write_reg(0x3, 0xf040);// OF uses 0xc040, but DS says bit 12 must be set spi_write_reg(0x8, 0); // vsync back porch (0=3H) spi_write_reg(0x9, 0); // hsync back porch (0=24clk) spi_write_reg(0x76, 0x2213);