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Correct audio clock

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9309 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Linus Nielsen Feltzing 2006-03-28 12:47:10 +00:00
parent ab5b179614
commit a8c1fb55a4
1 changed files with 2 additions and 2 deletions
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4
firmware/target/coldfire/iaudio/x5/system-x5.c
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@ -37,7 +37,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
PLLCR = 0x13442045; PLLCR = 0x13042045;
CSCR0 = 0x00001180; /* Flash: 4 wait states */ CSCR0 = 0x00001180; /* Flash: 4 wait states */
CSCR1 = 0x00000980; /* LCD: 2 wait states */ CSCR1 = 0x00000980; /* LCD: 2 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -54,7 +54,7 @@ void set_cpu_frequency(long frequency)
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
PLLCR = 0x16430045; PLLCR = 0x16030045;
CSCR0 = 0x00000580; /* Flash: 1 wait state */ CSCR0 = 0x00000580; /* Flash: 1 wait state */
CSCR1 = 0x00000180; /* LCD: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.