forked from len0rd/rockbox
x1000: Remove some #ifdef SPL in the sfc/nand code
Change-Id: I554d590bfa700e521a74b5216e09f9673902d676
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parent
423fcf951a
commit
16a1993cad
4 changed files with 12 additions and 29 deletions
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@ -25,11 +25,6 @@
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/* The max page size (main + spare) of all NAND chips used by this target */
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#define NAND_MAX_PAGE_SIZE (2048 + 64)
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/* The clock source to use for the SFC controller. Note the SPL has special
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* handling which ignores this choice, so it only applies to bootloader & app.
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*/
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#define NAND_CLOCK_SOURCE X1000_CLK_SCLK_A
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/* The clock speed to use for the SFC controller during chip identification */
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#define NAND_INIT_CLOCK_SPEED 150000000
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@ -73,7 +73,7 @@ int nand_open(void)
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/* Init hardware */
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sfc_open();
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sfc_set_dev_conf(NAND_INIT_SFC_DEV_CONF);
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sfc_set_clock(NAND_CLOCK_SOURCE, NAND_INIT_CLOCK_SPEED);
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sfc_set_clock(NAND_INIT_CLOCK_SPEED);
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/* Identify NAND chip */
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int status = 0;
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@ -103,7 +103,7 @@ int nand_open(void)
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/* Configure hardware and run init op */
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sfc_set_dev_conf(desc->data->dev_conf);
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sfc_set_clock(NAND_CLOCK_SOURCE, desc->data->clock_freq);
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sfc_set_clock(desc->data->clock_freq);
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if((status = desc->ops->open(&nand_driver)) < 0)
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goto _err;
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@ -33,18 +33,6 @@
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* simple, DMA is unconditionally disabled. */
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//#define NEED_SFC_DMA
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#if defined(BOOTLOADER_SPL)
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# if X1000_EXCLK_FREQ == 24000000
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# define FIXED_CLK_FREQ 600000000
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# define FIXED_CLK_SRC X1000_CLK_MPLL
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# elif X1000_EXCLK_FREQ == 26000000
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# define FIXED_CLK_FREQ 598000000
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# define FIXED_CLK_SRC X1000_CLK_MPLL
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# else
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# error "bad EXCLK freq"
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# endif
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#endif
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#define FIFO_THRESH 31
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#define SFC_STATUS_PENDING (-1)
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@ -111,16 +99,16 @@ void sfc_close(void)
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jz_writef(CPM_CLKGR, SFC(1));
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}
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void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq)
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void sfc_set_clock(uint32_t freq)
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{
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uint32_t in_freq;
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#ifdef FIXED_CLK_FREQ
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/* Small optimization to save code space in SPL by not polling clock */
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clksrc = FIXED_CLK_SRC;
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in_freq = FIXED_CLK_FREQ;
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#else
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in_freq = clk_get(clksrc);
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#endif
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/* TODO: This is a hack so we can use MPLL in the SPL.
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* There must be a better way to do this... */
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x1000_clk_t clksrc = X1000_CLK_MPLL;
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uint32_t in_freq = clk_get(clksrc);
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if(in_freq < freq) {
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clksrc = X1000_CLK_SCLK_A;
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in_freq = clk_get(clksrc);
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}
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uint32_t div = clk_calc_div(in_freq, freq);
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jz_writef(CPM_SSICDR, CE(1), CLKDIV(div - 1),
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@ -99,7 +99,7 @@ extern void sfc_close(void);
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#define sfc_set_wp_enable(en) \
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jz_writef(SFC_GLB, WP_EN((en) ? 1 : 0))
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extern void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq);
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extern void sfc_set_clock(uint32_t freq);
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/* Execute an operation. Returns zero on success, nonzero on failure. */
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extern int sfc_exec(const sfc_op* op);
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