forked from len0rd/rockbox
x1000: Rewrite clk_get code so it's more data driven
This is not pretty, but at least it should be usable by the SPL. Change-Id: I1c0cdb910109c882160e3effd7c778e4d961842c
This commit is contained in:
Aidan MacDonald
parent
20fc928221
commit
423fcf951a
2 changed files with 130 additions and 116 deletions
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@ -25,99 +25,129 @@
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#include "x1000/msc.h"
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#include "x1000/aic.h"
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static uint32_t pll_get(uint32_t pllreg, uint32_t onbit)
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struct clk_info {
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uint8_t mux_reg; /* offset from CPM_BASE for mux register */
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uint8_t mux_shift; /* shift to get mux */
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uint8_t mux_mask; /* mask to get mux after shifting */
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uint8_t mux_type; /* type of mux, maps register bits to clock source */
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uint8_t div_reg; /* offset from CPM_BASE for divider register */
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uint8_t div_shift; /* shift to get divider */
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uint8_t div_mask; /* mask to get divider after shifting */
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uint8_t miscbits; /* inclk shift, clkgr bit, and fake mux value */
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};
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/* Ugliness to pack/unpack stuff in clk_info->miscbits */
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#define INCLK_SHIFT(n) ((n) & 1)
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#define CLKGR_BIT(n) (((n) & 0x1f) << 1)
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#define FAKEMUX(n) (((n) & 3) << 6)
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#define GET_INCLK_SHIFT(miscbits) ((miscbits) & 1)
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#define GET_CLKGR_BIT(miscbits) (((miscbits) >> 1) & 0x1f)
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#define GET_FAKEMUX(miscbits) (((miscbits) >> 6) & 3)
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/* Clock sources -- the order here is important! */
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#define S_STOP 0
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#define S_EXCLK 1
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#define S_APLL 2
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#define S_MPLL 3
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#define S_SCLK_A 4
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/* Muxes */
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#define MUX_TWOBIT 0
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#define MUX_ONEBIT 1
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#define MUX_USB 2
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#define MUX_PHONY 3
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#define MUX_NUM_TYPES 4
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/* Ugliness to define muxes */
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#define MKSEL(x,i) (((x) & 0xf) << ((i)*4))
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#define GETSEL(x,i) (((x) >> ((i)*4)) & 0xf)
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#define STOP(i) MKSEL(S_STOP, i)
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#define EXCLK(i) MKSEL(S_EXCLK, i)
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#define APLL(i) MKSEL(S_APLL, i)
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#define MPLL(i) MKSEL(S_MPLL, i)
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#define SCLK_A(i) MKSEL(S_SCLK_A, i)
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#define MKMUX(a,b,c,d) (a(0)|b(1)|c(2)|d(3))
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/* Ugliness to shorten the clk_info table */
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#define JA(x) (JA_CPM_##x & 0xff)
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#define BM(x) ((BM_CPM_##x) >> (BP_CPM_##x))
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#define BP(x) (BP_CPM_##x)
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#define CG(x) CLKGR_BIT(BP_CPM_CLKGR_##x)
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#define M(r,f,t) JA(r), BP(r##_##f), BM(r##_##f), t
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#define D(r,f) JA(r), BP(r##_##f), BM(r##_##f)
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static const uint16_t clk_mux[MUX_NUM_TYPES] = {
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/* 00 01 10 11 */
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MKMUX(STOP, SCLK_A, MPLL, STOP), /* MUX_TWOBIT */
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MKMUX(SCLK_A, MPLL, STOP, STOP), /* MUX_ONEBIT */
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MKMUX(EXCLK, EXCLK, SCLK_A, MPLL), /* MUX_USB */
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MKMUX(EXCLK, APLL, MPLL, SCLK_A), /* MUX_PHONY */
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};
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/* Keep in order with enum x1000_clk_t */
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const struct clk_info clk_info[X1000_NUM_SIMPLE_CLKS] = {
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{0, 0, 0, MUX_PHONY, 0, 0, 0, CG(CPU_BIT)|FAKEMUX(0)},
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{0, 0, 0, MUX_PHONY, 0, 0, 0, CG(CPU_BIT)|FAKEMUX(1)},
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{0, 0, 0, MUX_PHONY, 0, 0, 0, CG(CPU_BIT)|FAKEMUX(2)},
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{0, 0, 0, MUX_PHONY, 0, 0, 0, CG(CPU_BIT)|FAKEMUX(3)},
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{M(CCR, SEL_CPLL, MUX_TWOBIT), D(CCR, CDIV), CG(CPU_BIT)},
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{M(CCR, SEL_CPLL, MUX_TWOBIT), D(CCR, L2DIV), CG(CPU_BIT)},
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{M(CCR, SEL_H0PLL, MUX_TWOBIT), D(CCR, H0DIV), CG(AHB0)},
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{M(CCR, SEL_H2PLL, MUX_TWOBIT), D(CCR, H2DIV), CG(APB0)},
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{M(CCR, SEL_H2PLL, MUX_TWOBIT), D(CCR, PDIV), CG(APB0)},
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{M(DDRCDR, CLKSRC, MUX_TWOBIT), D(DDRCDR, CLKDIV), CG(DDR)},
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{M(LPCDR, CLKSRC, MUX_ONEBIT), D(LPCDR, CLKDIV), CG(LCD)},
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{M(MSC0CDR, CLKSRC, MUX_ONEBIT), D(MSC0CDR, CLKDIV), CG(MSC0)|INCLK_SHIFT(1)},
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{M(MSC0CDR, CLKSRC, MUX_ONEBIT), D(MSC1CDR, CLKDIV), CG(MSC1)|INCLK_SHIFT(1)},
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{M(SSICDR, SFC_CS, MUX_ONEBIT), D(SSICDR, CLKDIV), CG(SFC)},
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{M(USBCDR, CLKSRC, MUX_USB), D(USBCDR, CLKDIV), CG(OTG)},
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};
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static uint32_t clk_get_in_rate(uint8_t mux_type, uint32_t mux)
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{
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if((pllreg & (1 << onbit)) == 0)
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uint32_t reg, onbit;
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uint32_t src = GETSEL(clk_mux[mux_type], mux);
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again:
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switch(src) {
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default: return 0;
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case S_EXCLK: return X1000_EXCLK_FREQ;
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case S_APLL: reg = REG_CPM_APCR; onbit = BM_CPM_APCR_ON; break;
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case S_MPLL: reg = REG_CPM_MPCR; onbit = BM_CPM_MPCR_ON; break;
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case S_SCLK_A: src = jz_readf(CPM_CCR, SEL_SRC); goto again;
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}
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if(!(reg & onbit))
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return 0;
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/* Both PLL registers share the same layout of N/M/OD bits.
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* The max multiplier is 128 and max EXCLK is 26 MHz, so the
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* multiplication should fit within 32 bits without overflow.
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*/
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uint32_t rate = X1000_EXCLK_FREQ;
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rate *= jz_vreadf(pllreg, CPM_APCR, PLLM) + 1;
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rate /= jz_vreadf(pllreg, CPM_APCR, PLLN) + 1;
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rate >>= jz_vreadf(pllreg, CPM_APCR, PLLOD);
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rate *= jz_vreadf(reg, CPM_APCR, PLLM) + 1;
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rate /= jz_vreadf(reg, CPM_APCR, PLLN) + 1;
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rate >>= jz_vreadf(reg, CPM_APCR, PLLOD);
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return rate;
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}
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static uint32_t sclk_a_get(void)
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static uint32_t clk_get_simple(const struct clk_info* info)
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{
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switch(jz_readf(CPM_CCR, SEL_SRC)) {
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case 1: return X1000_EXCLK_FREQ;
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case 2: return clk_get(X1000_CLK_APLL);
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default: return 0;
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}
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}
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static uint32_t ccr_get(uint32_t selbit, uint32_t divbit)
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{
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uint32_t reg = REG_CPM_CCR;
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uint32_t sel = (reg >> selbit) & 0x3;
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uint32_t div = (reg >> divbit) & 0xf;
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switch(sel) {
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case 1: return clk_get(X1000_CLK_SCLK_A) / (div + 1);
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case 2: return clk_get(X1000_CLK_MPLL) / (div + 1);
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default: return 0;
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}
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}
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static uint32_t ddr_get(void)
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{
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uint32_t reg = REG_CPM_DDRCDR;
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uint32_t div = jz_vreadf(reg, CPM_DDRCDR, CLKDIV);
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switch(jz_vreadf(reg, CPM_DDRCDR, CLKSRC)) {
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case 1: return clk_get(X1000_CLK_SCLK_A) / (div + 1);
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case 2: return clk_get(X1000_CLK_MPLL) / (div + 1);
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default: return 0;
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}
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}
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static uint32_t lcd_get(void)
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{
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if(jz_readf(CPM_CLKGR, LCD))
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if(REG_CPM_CLKGR & (1 << GET_CLKGR_BIT(info->miscbits)))
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return 0;
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uint32_t reg = REG_CPM_LPCDR;
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uint32_t rate;
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switch(jz_vreadf(reg, CPM_LPCDR, CLKSRC)) {
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case 0: rate = clk_get(X1000_CLK_SCLK_A); break;
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case 1: rate = clk_get(X1000_CLK_MPLL); break;
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default: return 0;
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}
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uint32_t base = 0xb0000000;
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uint32_t mux_reg = *(const volatile uint32_t*)(base + info->mux_reg);
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uint32_t div_reg = *(const volatile uint32_t*)(base + info->div_reg);
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rate /= jz_vreadf(reg, CPM_LPCDR, CLKDIV) + 1;
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uint32_t mux = (mux_reg >> info->mux_shift) & info->mux_mask;
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uint32_t div = (div_reg >> info->div_shift) & info->div_mask;
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mux |= GET_FAKEMUX(info->miscbits);
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uint32_t rate = clk_get_in_rate(info->mux_type, mux);
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rate >>= GET_INCLK_SHIFT(info->miscbits);
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rate /= (div + 1);
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return rate;
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}
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static uint32_t msc_get(int msc)
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{
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if((msc == 0 && jz_readf(CPM_CLKGR, MSC0)) ||
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(msc == 1 && jz_readf(CPM_CLKGR, MSC1)))
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return 0;
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uint32_t reg = REG_CPM_MSC0CDR;
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uint32_t rate;
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switch(jz_vreadf(reg, CPM_MSC0CDR, CLKSRC)) {
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case 0: rate = clk_get(X1000_CLK_SCLK_A); break;
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case 1: rate = clk_get(X1000_CLK_MPLL); break;
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default: return 0;
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}
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uint32_t div;
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if(msc == 0)
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div = jz_readf(CPM_MSC0CDR, CLKDIV);
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else
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div = jz_readf(CPM_MSC1CDR, CLKDIV);
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rate /= 2 * (div + 1);
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rate >>= REG_MSC_CLKRT(msc);
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return rate;
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}
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static uint32_t i2s_mclk_get(void)
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#ifndef BOOTLOADER
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static uint32_t clk_get_i2s_mclk(void)
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{
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if(jz_readf(CPM_CLKGR, AIC))
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return 0;
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@ -143,48 +173,29 @@ static uint32_t i2s_mclk_get(void)
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return rate;
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}
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static uint32_t i2s_bclk_get(void)
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static uint32_t clk_get_i2s_bclk(void)
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{
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return i2s_mclk_get() / (REG_AIC_I2SDIV + 1);
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return clk_get_i2s_mclk() / (REG_AIC_I2SDIV + 1);
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}
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static uint32_t sfc_get(void)
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static uint32_t clk_get_decimal(x1000_clk_t clk)
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{
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if(jz_readf(CPM_CLKGR, SFC))
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return 0;
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uint32_t reg = REG_CPM_SSICDR;
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uint32_t rate;
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if(jz_vreadf(reg, CPM_SSICDR, SFC_CS) == 0)
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rate = clk_get(X1000_CLK_SCLK_A);
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else
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rate = clk_get(X1000_CLK_MPLL);
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rate /= jz_vreadf(reg, CPM_SSICDR, CLKDIV) + 1;
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return rate;
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switch(clk) {
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case X1000_CLK_I2S_MCLK: return clk_get_i2s_mclk();
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case X1000_CLK_I2S_BCLK: return clk_get_i2s_bclk();
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default: return 0;
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}
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}
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#endif
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uint32_t clk_get(x1000_clk_t clk)
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{
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switch(clk) {
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case X1000_CLK_EXCLK: return X1000_EXCLK_FREQ;
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case X1000_CLK_APLL: return pll_get(REG_CPM_APCR, BP_CPM_APCR_ON);
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case X1000_CLK_MPLL: return pll_get(REG_CPM_MPCR, BP_CPM_MPCR_ON);
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case X1000_CLK_SCLK_A: return sclk_a_get();
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case X1000_CLK_CPU: return ccr_get(BP_CPM_CCR_SEL_CPLL, BP_CPM_CCR_CDIV);
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case X1000_CLK_L2CACHE: return ccr_get(BP_CPM_CCR_SEL_CPLL, BP_CPM_CCR_L2DIV);
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case X1000_CLK_AHB0: return ccr_get(BP_CPM_CCR_SEL_H0PLL, BP_CPM_CCR_H0DIV);
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case X1000_CLK_AHB2: return ccr_get(BP_CPM_CCR_SEL_H2PLL, BP_CPM_CCR_H2DIV);
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case X1000_CLK_PCLK: return ccr_get(BP_CPM_CCR_SEL_H2PLL, BP_CPM_CCR_PDIV);
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case X1000_CLK_DDR: return ddr_get();
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case X1000_CLK_LCD: return lcd_get();
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case X1000_CLK_MSC0: return msc_get(0);
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case X1000_CLK_MSC1: return msc_get(1);
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case X1000_CLK_I2S_MCLK: return i2s_mclk_get();
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case X1000_CLK_I2S_BCLK: return i2s_bclk_get();
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case X1000_CLK_SFC: return sfc_get();
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default: return 0;
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}
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#ifndef BOOTLOADER
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if(clk >= X1000_NUM_SIMPLE_CLKS)
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return clk_get_decimal(clk);
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#endif
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return clk_get_simple(&clk_info[clk]);
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}
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const char* clk_get_name(x1000_clk_t clk)
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@ -204,9 +215,10 @@ const char* clk_get_name(x1000_clk_t clk)
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CASE(LCD);
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CASE(MSC0);
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CASE(MSC1);
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CASE(SFC);
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CASE(USB);
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CASE(I2S_MCLK);
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CASE(I2S_BCLK);
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CASE(SFC);
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#undef CASE
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default:
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return "NONE";
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@ -45,9 +45,11 @@ typedef enum x1000_clk_t {
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X1000_CLK_LCD,
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X1000_CLK_MSC0,
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X1000_CLK_MSC1,
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X1000_CLK_I2S_MCLK,
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X1000_CLK_I2S_BCLK,
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X1000_CLK_SFC,
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X1000_CLK_USB,
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X1000_NUM_SIMPLE_CLKS,
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X1000_CLK_I2S_MCLK = X1000_NUM_SIMPLE_CLKS,
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X1000_CLK_I2S_BCLK,
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X1000_CLK_COUNT,
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} x1000_clk_t;
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