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H110/H115: Slightly longer initial SDRAM refresh cycle, correct comment.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7639 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2005-10-18 19:35:31 +00:00
parent 127f069545
commit 09b4743707
1 changed files with 1 additions and 1 deletions
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2
firmware/crt0.S
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@ -191,7 +191,7 @@ irq_handler:
/* Set up the DRAM controller. The refresh is based on the 11.2896MHz /* Set up the DRAM controller. The refresh is based on the 11.2896MHz
clock (5.6448MHz bus frequency). We haven't yet started the PLL */ clock (5.6448MHz bus frequency). We haven't yet started the PLL */
#if MEM < 32 #if MEM < 32
move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */ move.w #0x8204,%d0 /* DCR - Synchronous, 80 cycle refresh */
#else #else
move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */
#endif #endif