From 09b4743707ca2acb86abd96816f62663b79a99df Mon Sep 17 00:00:00 2001
From: Jens Arnold <amiconn@rockbox.org>
Date: Tue, 18 Oct 2005 19:35:31 +0000
Subject: [PATCH] H110/H115: Slightly longer initial SDRAM refresh cycle,
 correct comment.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7639 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/crt0.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/firmware/crt0.S b/firmware/crt0.S
index e903bc9ddf..6cec3ec3ce 100644
--- a/firmware/crt0.S
+++ b/firmware/crt0.S
@@ -191,7 +191,7 @@ irq_handler:
     /* Set up the DRAM controller. The refresh is based on the 11.2896MHz
        clock (5.6448MHz bus frequency). We haven't yet started the PLL */
 #if MEM < 32
-    move.w  #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */
+    move.w  #0x8204,%d0 /* DCR - Synchronous, 80 cycle refresh */
 #else
     move.w  #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */
 #endif