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591 lines
17 KiB
C
591 lines
17 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: system-s5l8700.c 28935 2010-12-30 20:23:46Z Buschel $
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*
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* Copyright (C) 2007 by Rob Purchase
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "system-target.h"
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#include "i2c-s5l8702.h"
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#include "pmu-target.h"
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#include "uart-target.h"
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#include "gpio-s5l8702.h"
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#include "dma-s5l8702.h"
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#include "clocking-s5l8702.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked, \
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weak, alias("fiq_dummy")));
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default_interrupt(INT_EXT0); /* GPIOIC group 6 (GPIO 0..31) */
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default_interrupt(INT_EXT1); /* GPIOIC group 5 (GPIO 32..63) */
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default_interrupt(INT_EXT2); /* GPIOIC group 4 (GPIO 64..95) */
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default_interrupt(INT_EXT3); /* GPIOIC group 3 (GPIO 96..123) */
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default_interrupt(INT_IRQ4);
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default_interrupt(INT_IRQ5);
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default_interrupt(INT_IRQ6);
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default_interrupt(INT_TIMERE); /* IRQ7: 32-bit timers */
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default_interrupt(INT_TIMERF);
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default_interrupt(INT_TIMERG);
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default_interrupt(INT_TIMERH);
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default_interrupt(INT_TIMERA); /* IRQ8: 16-bit timers */
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default_interrupt(INT_TIMERB);
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default_interrupt(INT_TIMERC);
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default_interrupt(INT_TIMERD);
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default_interrupt(INT_IRQ9);
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default_interrupt(INT_IRQ10);
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default_interrupt(INT_IRQ11);
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default_interrupt(INT_IRQ12);
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default_interrupt(INT_IRQ13);
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default_interrupt(INT_IRQ14);
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default_interrupt(INT_IRQ15);
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default_interrupt(INT_DMAC0);
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default_interrupt(INT_DMAC1);
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default_interrupt(INT_IRQ18);
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default_interrupt(INT_USB_FUNC);
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default_interrupt(INT_IRQ20);
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default_interrupt(INT_IRQ21);
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default_interrupt(INT_IRQ22);
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default_interrupt(INT_WHEEL);
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default_interrupt(INT_UART0);
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default_interrupt(INT_UART1);
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default_interrupt(INT_UART2);
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default_interrupt(INT_UART3);
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default_interrupt(INT_IRQ28); /* obsolete/not implemented UART4 ??? */
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default_interrupt(INT_ATA);
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default_interrupt(INT_IRQ30);
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default_interrupt(INT_EXT4); /* GPIOIC group 2 (not used) */
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default_interrupt(INT_EXT5); /* GPIOIC group 1 (not used) */
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default_interrupt(INT_EXT6); /* GPIOIC group 0 */
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default_interrupt(INT_IRQ34);
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default_interrupt(INT_IRQ35);
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default_interrupt(INT_IRQ36);
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default_interrupt(INT_IRQ37);
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default_interrupt(INT_IRQ38);
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default_interrupt(INT_IRQ39);
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default_interrupt(INT_IRQ40);
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default_interrupt(INT_IRQ41);
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default_interrupt(INT_IRQ42);
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default_interrupt(INT_IRQ43);
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default_interrupt(INT_MMC);
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default_interrupt(INT_IRQ45);
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default_interrupt(INT_IRQ46);
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default_interrupt(INT_IRQ47);
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default_interrupt(INT_IRQ48);
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default_interrupt(INT_IRQ49);
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default_interrupt(INT_IRQ50);
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default_interrupt(INT_IRQ51);
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default_interrupt(INT_IRQ52);
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default_interrupt(INT_IRQ53);
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default_interrupt(INT_IRQ54);
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default_interrupt(INT_IRQ55);
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default_interrupt(INT_IRQ56);
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default_interrupt(INT_IRQ57);
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default_interrupt(INT_IRQ58);
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default_interrupt(INT_IRQ59);
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default_interrupt(INT_IRQ60);
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default_interrupt(INT_IRQ61);
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default_interrupt(INT_IRQ62);
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default_interrupt(INT_IRQ63);
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static int current_irq;
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static const struct clocking_mode clk_modes[] =
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{
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/* cdiv hdiv hprat hsdiv */ /* CClk HClk PClk SM1Clk FPS */
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{ 1, 2, 2, 4 }, /* 216 108 54 27 42 */
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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{ 4, 4, 2, 2 }, /* 54 54 27 27 21 */
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#endif
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};
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#define N_CLK_MODES (sizeof(clk_modes) / sizeof(struct clocking_mode))
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enum {
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CLK_BOOST = 0,
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CLK_UNBOOST = N_CLK_MODES - 1,
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};
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void INT_TIMER(void) ICODE_ATTR;
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void INT_TIMER()
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{
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if (TACON & (TACON >> 4) & 0x7000) INT_TIMERA();
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if (TBCON & (TBCON >> 4) & 0x7000) INT_TIMERB();
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if (TCCON & (TCCON >> 4) & 0x7000) INT_TIMERC();
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if (TDCON & (TDCON >> 4) & 0x7000) INT_TIMERD();
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}
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void INT_TIMER32(void) ICODE_ATTR;
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void INT_TIMER32()
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{
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uint32_t tstat = TSTAT;
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if ((TECON >> 12) & 0x7 & (tstat >> 24)) INT_TIMERE();
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if ((TFCON >> 12) & 0x7 & (tstat >> 16)) INT_TIMERF();
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if ((TGCON >> 12) & 0x7 & (tstat >> 8)) INT_TIMERG();
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if ((THCON >> 12) & 0x7 & tstat) INT_TIMERH();
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}
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static void (* const irqvector[])(void) =
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{
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INT_EXT0,INT_EXT1,INT_EXT2,INT_EXT3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_TIMER32,
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INT_TIMER,INT_IRQ9,INT_IRQ10,INT_IRQ11,INT_IRQ12,INT_IRQ13,INT_IRQ14,INT_IRQ15,
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INT_DMAC0,INT_DMAC1,INT_IRQ18,INT_USB_FUNC,INT_IRQ20,INT_IRQ21,INT_IRQ22,INT_WHEEL,
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INT_UART0,INT_UART1,INT_UART2,INT_UART3,INT_IRQ28,INT_ATA,INT_IRQ30,INT_EXT4,
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INT_EXT5,INT_EXT6,INT_IRQ34,INT_IRQ35,INT_IRQ36,INT_IRQ37,INT_IRQ38,INT_IRQ39,
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INT_IRQ40,INT_IRQ41,INT_IRQ42,INT_IRQ43,INT_MMC,INT_IRQ45,INT_IRQ46,INT_IRQ47,
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INT_IRQ48,INT_IRQ49,INT_IRQ50,INT_IRQ51,INT_IRQ52,INT_IRQ53,INT_IRQ54,INT_IRQ55,
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INT_IRQ56,INT_IRQ57,INT_IRQ58,INT_IRQ59,INT_IRQ60,INT_IRQ61,INT_IRQ62,INT_IRQ63
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};
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static void UIRQ(void)
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{
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panicf("Unhandled IRQ %d!", current_irq);
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}
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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const void* dummy0 = VIC0ADDRESS;
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(void)dummy0;
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const void* dummy1 = VIC1ADDRESS;
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(void)dummy1;
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uint32_t irqs0 = VIC0IRQSTATUS;
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uint32_t irqs1 = VIC1IRQSTATUS;
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for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1)
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if (irqs0 & 1)
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irqvector[current_irq]();
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for (current_irq = 32; irqs1; current_irq++, irqs1 >>= 1)
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if (irqs1 & 1)
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irqvector[current_irq]();
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VIC0ADDRESS = NULL;
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VIC1ADDRESS = NULL;
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_dummy(void)
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{
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asm volatile (
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"subs pc, lr, #4 \r\n"
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);
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}
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static void vic_init(void)
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{
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/* reset VIC controller */
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VIC0INTENCLEAR = ~0;
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VIC1INTENCLEAR = ~0;
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VIC0ADDRESS = (void*)0xffffffff;
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VIC1ADDRESS = (void*)0xffffffff;
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VIC0EDGE1 = ~0;
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VIC1EDGE1 = ~0;
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}
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void system_init(void)
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{
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/*
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* Bootloader seems to give a blank screen when IRAM1 is disabled
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* - FW 10/13/19
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*/
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#ifndef BOOTLOADER
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/* disable IRAM1 (not used because it is slower than DRAM) */
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clockgate_enable(CLOCKGATE_SM1, false);
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#endif
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clocking_init(clk_modes, 0);
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#ifndef BOOTLOADER
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gpio_preinit();
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i2c_preinit(0);
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pmu_preinit();
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#endif
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gpio_init();
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eint_init();
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vic_init();
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dma_init();
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#ifdef HAVE_SERIAL
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uart_init();
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#endif
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VIC0INTENABLE = 1 << IRQ_WHEEL;
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VIC0INTENABLE = 1 << IRQ_TIMER;
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VIC0INTENABLE = 1 << IRQ_TIMER32;
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#if defined(IPOD_6G)
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VIC0INTENABLE = 1 << IRQ_ATA;
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VIC1INTENABLE = 1 << (IRQ_MMC - 32);
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#endif
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}
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void system_reboot(void)
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{
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/* Reset the SoC */
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asm volatile("msr CPSR_c, #0xd3 \n"
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"mov r0, #0x100000 \n");
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asm volatile("str r0, [%0] \n" : : "r"(WDT_BASE));
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/* Wait for reboot to kick in */
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while(1);
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}
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//extern void post_mortem_stub(void);
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void system_exception_wait(void)
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{
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// post_mortem_stub();
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while(1);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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if (cpu_frequency == frequency)
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return;
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if (frequency == CPUFREQ_MAX)
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{
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pmu_set_cpu_voltage(true); /* high */
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set_clocking_level(CLK_BOOST);
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}
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else
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{
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set_clocking_level(CLK_UNBOOST);
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pmu_set_cpu_voltage(false); /* low */
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}
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cpu_frequency = frequency;
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}
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#endif
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static void set_page_tables(void)
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{
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/* map RAM to itself and enable caching for it */
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map_section(0, 0, 0x380, CACHE_ALL);
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#ifdef IPOD_NANO4G
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/* map system vector addresses to IRAM0 */
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map_section(IRAM0_ORIG, 0, 1, CACHE_ALL);
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#endif
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/* disable caching for I/O area */
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map_section(IO_BASE, IO_BASE, 0x80, CACHE_NONE);
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/* map RAM uncached addresses */
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map_section(0, S5L8702_UNCACHED_ADDR(0x0), 0x380, CACHE_NONE);
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}
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void memory_init(void)
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{
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ttb_init();
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set_page_tables();
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enable_mmu();
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}
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#ifdef BOOTLOADER
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#include <stdbool.h>
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static void syscon_preinit(void)
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{
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/* after ROM boot, CG16_SYS is using PLL0 @108 MHz
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CClk = 108 MHz, HClk = 54 MHz, PClk = 27 MHz */
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#if CONFIG_CPU == S5L8702
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CLKCON0 &= ~CLKCON0_SDR_DISABLE_BIT;
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#elif CONFIG_CPU == S5L8720
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int sec_epoch = soc_get_sec_epoch();
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PWRCON(0) = 0x327e5;
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PWRCON(1) = 0xfe2bed6d;
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PWRCON(2) = 0x73;
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PWRCON(3) = 0xff;
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PWRCON(4) = 0xdcf779;
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if (sec_epoch)
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CLKCON0 &= ~CLKCON0_SDR_DISABLE_BIT;
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else
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CLKCON0 |= CLKCON0_SDR_DISABLE_BIT;
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#endif
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PLLMODE &= ~PLLMODE_OSCSEL_BIT; /* CG16_SEL_OSC = OSC0 */
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#if CONFIG_CPU == S5L8702
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cg16_config(&CG16_SYS, true, CG16_SEL_OSC, 1, 1);
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soc_set_system_divs(1, 1, 1);
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#elif CONFIG_CPU == S5L8720
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cg16_config(&CG16_SYS, true, CG16_SEL_OSC, 1, 1, 0x0);
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// soc_set_system_divs(1, 1, 1);
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CLKCON1 = 0;
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while (CLKCON1);
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#endif
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/* stop all PLLs */
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for (int pll = 0; pll < 3; pll++)
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pll_onoff(pll, false);
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#if CONFIG_CPU == S5L8702
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pll_config(2, PLLOP_DM, 1, 36, 1, 32400);
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pll_onoff(2, true);
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soc_set_system_divs(1, 2, 2 /*hprat*/);
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#elif CONFIG_CPU == S5L8720
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PLLUNK3C = 0;
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pll_config(0, PLLOP_DM, sec_epoch ? 6 : 3, 133, 1, 39900);
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pll_onoff(0, true);
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// soc_set_system_divs(1, 2, 1 /*hprat*/);
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// XXX: Without this, SDRAM does not work!
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uint32_t val = 0x404040;
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CLKCON1 = val;
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while (CLKCON1 != val);
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CLKCON0 |= CLKCON0_UNK30_BIT;
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#endif
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#if CONFIG_CPU == S5L8702
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cg16_config(&CG16_SYS, true, CG16_SEL_PLL2, 1, 1);
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cg16_config(&CG16_2L, false, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_SVID, false, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_AUD0, false, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_AUD1, false, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_AUD2, false, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_5L, false, CG16_SEL_OSC, 1, 1);
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#elif CONFIG_CPU == S5L8720
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cg16_config(&CG16_SYS, true, CG16_SEL_PLL0, 1, 1, 0x0);
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cg16_config(&CG16_LCD, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_SVID, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_AUD0, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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cg16_config(&CG16_AUD1, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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cg16_config(&CG16_AUD2, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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// TODO: configure a 12 MHz ECLK for all targets, so the timer settings will be the same.
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// cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, (S5L8720_OSC0_HZ / ECLK), 1, 0);
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cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_5L, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_6L, false, CG16_SEL_OSC, 1, 1, 0x0);
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#endif
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soc_set_hsdiv(1);
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#if CONFIG_CPU == S5L8702
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PWRCON_AHB = ~((1 << CLOCKGATE_SMx) |
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(1 << CLOCKGATE_SM1));
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PWRCON_APB = ~((1 << (CLOCKGATE_TIMER - 32)) |
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(1 << (CLOCKGATE_GPIO - 32)));
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#endif
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}
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static void miu_preinit(bool selfrefreshing)
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{
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#if CONFIG_CPU == S5L8702
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if (selfrefreshing)
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MIUCON = 0x11; /* TBC: self-refresh -> IDLE */
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#ifdef IPOD_6G
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MIUCON = 0x80D; /* remap = 1 (IRAM mapped to 0x0),
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TBC: SDRAM bank and column configuration */
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#elif defined(IPOD_NANO3G)
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MIUCON = 0x1000100D;
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#endif
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MIU_REG(0xF0) = 0x0;
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#ifdef IPOD_6G
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MIUAREF = 0x6105D; /* Auto-Refresh enabled,
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Row refresh interval = 0x5d/12MHz = 7.75 uS */
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#elif defined(IPOD_NANO3G)
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MIUAREF = 0x4105D;
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#endif
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// TODO?
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// MIUAREF = 0x5D;
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MIUSDPARA = 0x1FB621;
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MIU_REG(0x200) = 0x1845;
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MIU_REG(0x204) = 0x1845;
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MIU_REG(0x210) = 0x1800;
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MIU_REG(0x214) = 0x1800;
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MIU_REG(0x220) = 0x1845;
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MIU_REG(0x224) = 0x1845;
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MIU_REG(0x230) = 0x1885;
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MIU_REG(0x234) = 0x1885;
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MIU_REG(0x14) = 0x19; /* TBC: 2^19 = 0x2000000 = SDRAMSIZE (32Mb) */
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MIU_REG(0x18) = 0x19; /* TBC: 2^19 = 0x2000000 = SDRAMSIZE (32Mb) */
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MIU_REG(0x1C) = 0x790682B;
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MIU_REG(0x314) &= ~0x10;
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|
|
for (int i = 0; i < 0x24; i++)
|
|
MIU_REG(0x2C + i*4) &= ~(1 << 24);
|
|
|
|
MIU_REG(0x1CC) = 0x540;
|
|
MIU_REG(0x1D4) |= 0x80;
|
|
|
|
MIUCOM = 0x33; /* No action CMD */
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x233; /* Precharge all banks CMD */
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x333; /* Auto-refresh CMD */
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x333; /* Auto-refresh CMD */
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
|
|
if (!selfrefreshing)
|
|
{
|
|
MIUMRS = 0x33; /* MRS: Bust Length = 8, CAS = 3 */
|
|
MIUCOM = 0x133; /* Mode Register Set CMD */
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUMRS = 0x8040; /* EMRS: Strength = 1/4, Self refresh area = Full */
|
|
MIUCOM = 0x133; /* Mode Register Set CMD */
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
}
|
|
|
|
MIUAREF |= 0x61000; /* Auto-refresh enabled */
|
|
#elif CONFIG_CPU == S5L8720
|
|
// TODO: There are things wrong, copying from spireader
|
|
GPIOUNK384 = 0;
|
|
|
|
MIU_REG(0) = 1;
|
|
MIU_REG(0x100) = 0x1030;
|
|
MIU_REG(0x11C) = 0xFF;
|
|
MIU_REG(0x120) = 0xFF;
|
|
|
|
MIU_REG(0x114) = 0x8AAC25;
|
|
MIU_REG(0x124) = 0x50D67E5;
|
|
MIU_REG(0x118) = 0x8;
|
|
MIU_REG(0x108) = 0x2000B;
|
|
MIU_REG(0x148) = 0x4;
|
|
MIU_REG(0x14C) = 0x0;
|
|
|
|
MIU_REG(0x140) = 0x3B3B2;
|
|
while (!(MIU_REG(0x140) & 0x2));
|
|
MIU_REG(0x140) = 0x3B3B3;
|
|
|
|
//while ((MIU_REG(0x144) & 0x3) != 3); // TBC
|
|
while (~MIU_REG(0x144) & 0x3); // TBC
|
|
MIU_REG(0x140) = ((MIU_REG(0x144) << 2) & 0x0ff00000) + 0xff53b3b0;
|
|
MIU_REG(0x150) = 0x10;
|
|
|
|
if (selfrefreshing) {
|
|
MIUCOM = 0x11; /* TBC: self-refresh -> IDLE */ // XXX: the s5l8702 does MIU_REG(0) = MIUCO_N_ = 0x11
|
|
}
|
|
else {
|
|
MIUCOM = 0x33; /* No action CMD */
|
|
MIUCOM = 0x233; /* Precharge all banks CMD */
|
|
while (MIUCOM & 0x110000);
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x333; /* Auto-refresh CMD */
|
|
while (MIUCOM & 0x110000);
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x333; /* Auto-refresh CMD */
|
|
while (MIUCOM & 0x110000);
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUMRS = 0x33; /* MRS: Bust Length = 8, CAS = 3 */
|
|
MIUCOM = 0x133; /* Mode Register Set CMD */
|
|
while (MIUCOM & 0x110000);
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
MIUMRS = 0x8040; /* EMRS: Strength = 1/4, Self refresh area = Full */
|
|
MIUCOM = 0x133; /* Mode Register Set CMD */
|
|
while (MIUCOM & 0x110000);
|
|
MIUCOM = 0x33;
|
|
MIUCOM = 0x33;
|
|
// MIUCOM = 0x33;
|
|
}
|
|
|
|
MIUCOM = 0x33;
|
|
|
|
MIU_REG(0x10C) = 0x40;
|
|
MIU_REG(0x100) |= 0x9100000;
|
|
MIU_REG(0x11C) = 0x19;
|
|
MIU_REG(0x120) = 0x1;
|
|
MIU_REG(0x108) = 0x2100B; // TBC: MIUAREF?, 0xb/12MHz = 1 uS, 0xb/24MHz = 0.5uS
|
|
MIU_REG(0x8) = 0x1;
|
|
|
|
UNK3E000008 = 0x1f;
|
|
#endif
|
|
}
|
|
|
|
/* Preliminary HW initialization */
|
|
void system_preinit(void)
|
|
{
|
|
bool hibernated; // TODO: hibernated -> resuming, or perhaps better warmboot
|
|
#if CONFIG_CPU == S5L8720
|
|
uint32_t boot_config;
|
|
|
|
/* Read boot configuration on PDAT3:
|
|
* [7:5] -> select 2nd boot media (NOR0, NOR1 or NAND)
|
|
* [4:3] -> unknown
|
|
* [2] -> unknown
|
|
*/
|
|
PCON3 &= ~0xffffff00;
|
|
udelay(1000);
|
|
boot_config = PDAT3 >> 2;
|
|
#endif
|
|
|
|
syscon_preinit();
|
|
gpio_preinit();
|
|
i2c_preinit(0);
|
|
|
|
#if CONFIG_CPU == S5L8720
|
|
/* TBC: store boot config into a PMU memory register */
|
|
pmu_wr(0x7f, boot_config);
|
|
#endif
|
|
hibernated = pmu_is_hibernated();
|
|
|
|
pmu_preinit();
|
|
|
|
miu_preinit(hibernated);
|
|
}
|
|
|
|
#endif /* BOOTLOADER */
|