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5ddfdf6e2f
Set number of FSR edges required for DPLL/ASRC lock Set DPLL bandwidth larger Both should help prevent dropouts, especially with sample rates >=96khz Credit to ZappBranigan2972 on the forums Change-Id: I55a90d44ac7fcec5894377e32cdadad66bb05610
208 lines
No EOL
6.9 KiB
C
208 lines
No EOL
6.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald, Dana Conrad
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "audiohw.h"
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#include "pcm_sw_volume.h"
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#include "pcm_sampr.h"
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#include "i2c-target.h"
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#include "button.h"
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// #define LOGF_ENABLE
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#include "logf.h"
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#include "aic-x1000.h"
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#include "i2c-x1000.h"
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#include "gpio-x1000.h"
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/*
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* Earlier devices audio path appears to be:
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* DAC \--> HP Amp --> Stereo Switch --> HP OUT
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* \-> LO OUT
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*
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* Recent devices, the audio path seems to have changed to:
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* DAC --> HP Amp --> Stereo Switch \--> HP OUT
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* \-> LO OUT
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*/
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void audiohw_init(void)
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{
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/* explicitly mute everything */
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gpio_set_level(GPIO_HPAMP_SHDN, 0);
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gpio_set_level(GPIO_STEREOSW_MUTE, 1);
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gpio_set_level(GPIO_DAC_PWR, 0);
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aic_set_play_last_sample(true);
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aic_set_external_codec(true);
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aic_set_i2s_mode(AIC_I2S_MASTER_MODE);
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audiohw_set_frequency(HW_FREQ_48);
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aic_enable_i2s_master_clock(true);
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aic_enable_i2s_bit_clock(true);
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mdelay(10);
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/* power on DAC and HP Amp */
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gpio_set_level(GPIO_DAC_ANALOG_PWR, 1);
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gpio_set_level(GPIO_HPAMP_POWER, 1);
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}
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void audiohw_postinit(void)
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{
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/*
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* enable playback, fill FIFO buffer with -1 to prevent
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* the DAC from auto-muting, wait, and then stop playback.
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* This seems to completely prevent power-on or first-track
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* clicking.
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*/
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jz_writef(AIC_CCR, ERPL(1));
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for (int i = 0; i < 32; i++)
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{
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jz_write(AIC_DR, 0xFFFFFF);
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}
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/* Wait until all samples are through the FIFO. */
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while(jz_readf(AIC_SR, TFL) != 0);
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mdelay(20); /* This seems to silence the power-on click */
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jz_writef(AIC_CCR, ERPL(0));
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/* unmute - attempt to make power-on pop-free */
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gpio_set_level(GPIO_STEREOSW_SEL, 0);
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gpio_set_level(GPIO_HPAMP_SHDN, 1);
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mdelay(10);
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gpio_set_level(GPIO_DAC_PWR, 1);
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mdelay(10);
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gpio_set_level(GPIO_STEREOSW_MUTE, 0);
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i2c_x1000_set_freq(ES9018K2M_BUS, I2C_FREQ_400K);
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int ret = es9018k2m_read_reg(ES9018K2M_REG0_SYSTEM_SETTINGS);
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if (ret >= 0) /* Detected ES9018K2M DAC */
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{
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logf("ES9018K2M found: ret=%d", ret);
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es9018k2m_present_flag = 1;
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/* Default is 32-bit data, and it works ok. Enabling the following
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* causes issue. Which is weird, I definitely thought AIC was configured
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* for 24-bit data... */
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// es9018k2m_write_reg(ES9018K2M_REG1_INPUT_CONFIG, 0b01001100); // 24-bit data
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/* Datasheet: Sets the number os FSR edges that must occur before *
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* the DPLL and ASRC can lock on to the the incoming Signal. *
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* When Samplerates >= 96khz could be used, STOP_DIV should be set *
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* to 0 (= 16384 FSR Edges). *
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* Reg #10 [3:0] (0x05 default, 2730 FSR Edges) */
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es9018k2m_write_reg(ES9018K2M_REG10_MASTER_MODE_CTRL, 0x00);
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/* Datasheet: The ES90x8Q2M/K2M contains a Jitter Eliminator block, *
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* which employs the use of a digital phase locked loop (DPLL) to *
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* lock to the incoming audio clock rate. When in I2S or SPDIF mode, *
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* the DPLL will lock to the frame clock (1 x fs). However, when in *
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* DSD mode, the DPLL has no frame clock information, and must in- *
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* stead lock to the bit clock rate (BCK). For this reason, there are *
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* two bandwidth settings for the DPLL. *
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Reg #12 [7:4] (0x05 default) bandwidth for I2S / SPDIF mode.
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Reg #12 [3:0] (0x0A default) bandwidth for DSD mode.
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* The DPLL bandwidth sets how quickly the DPLL can adjust its intern *
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* representation of the audio clock. The higher the jitter or *
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* frequency drift on the audio clock, the higher the bandwidth must *
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* be so that the DPLL can react. *
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* ! If the bandwidth is “too low”, the DPLL will loose lock and you *
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* ! will hear random dropouts. (Fixed my SurfansF20 v3.2 dropouts) */
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es9018k2m_write_reg(ES9018K2M_REG12_DPLL_SETTINGS, 0xda);
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} else { /* Default to SWVOL for PCM5102A DAC */
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logf("Default to SWVOL: ret=%d", ret);
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}
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}
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void audiohw_close(void)
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{
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/* mute - attempt to make power-off pop-free */
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gpio_set_level(GPIO_STEREOSW_MUTE, 1);
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mdelay(10);
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gpio_set_level(GPIO_DAC_PWR, 0);
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mdelay(10);
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gpio_set_level(GPIO_HPAMP_SHDN, 0);
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}
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void audiohw_set_frequency(int fsel)
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{
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int sampr = hw_freq_sampr[fsel];
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int mult = 256;
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aic_enable_i2s_bit_clock(false);
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aic_set_i2s_clock(X1000_CLK_SCLK_A, sampr, mult);
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aic_enable_i2s_bit_clock(true);
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}
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void audiohw_set_volume(int vol_l, int vol_r)
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{
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int l, r;
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eros_qn_set_last_vol(vol_l, vol_r);
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l = vol_l;
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r = vol_r;
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#if (defined(HAVE_HEADPHONE_DETECTION) && defined(HAVE_LINEOUT_DETECTION))
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/* Due to the hardware's detection method, make the Line-Out
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* the default. The LO can only be detected if it is active
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* (assuming a high-impedance device is attached). HP takes priority
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* if both are present. */
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if (headphones_inserted())
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{
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eros_qn_switch_output(0);
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}
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else
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{
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eros_qn_switch_output(1);
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l = r = eros_qn_get_volume_limit();
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}
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#endif
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if (es9018k2m_present_flag) /* ES9018K2M */
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{
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/* Same volume range and mute point for both DACs, so use PCM5102A_VOLUME_MIN */
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l = l <= PCM5102A_VOLUME_MIN ? PCM_MUTE_LEVEL : l;
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r = r <= PCM5102A_VOLUME_MIN ? PCM_MUTE_LEVEL : r;
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/* set software volume just below unity due to
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* DAC offset. We don't want to overflow the PCM system. */
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pcm_set_master_volume(-1, -1);
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es9018k2m_set_volume_async(l, r);
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}
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else /* PCM5102A */
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{
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l = l <= PCM5102A_VOLUME_MIN ? PCM_MUTE_LEVEL : (l / 20);
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r = r <= PCM5102A_VOLUME_MIN ? PCM_MUTE_LEVEL : (r / 20);
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pcm_set_master_volume(l, r);
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}
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}
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void audiohw_set_filter_roll_off(int value)
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{
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if (es9018k2m_present_flag)
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{
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es9018k2m_set_filter_roll_off(value);
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}
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} |