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Set number of FSR edges required for DPLL/ASRC lock Set DPLL bandwidth larger Both should help prevent dropouts, especially with sample rates >=96khz Credit to ZappBranigan2972 on the forums Change-Id: I55a90d44ac7fcec5894377e32cdadad66bb05610 |
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| .. | ||
| adc-target.h | ||
| audiohw-erosqnative.c | ||
| backlight-erosqnative.c | ||
| backlight-target.h | ||
| button-erosqnative.c | ||
| button-target.h | ||
| gpio-target.h | ||
| i2c-target.h | ||
| lcd-erosqnative.c | ||
| power-erosqnative.c | ||