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Set number of FSR edges required for DPLL/ASRC lock Set DPLL bandwidth larger Both should help prevent dropouts, especially with sample rates >=96khz Credit to ZappBranigan2972 on the forums Change-Id: I55a90d44ac7fcec5894377e32cdadad66bb05610 |
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| .. | ||
| ingenic_jz47xx | ||
| ingenic_x1000 | ||
| exception-mips.S | ||
| mipsr2-endian.h | ||
| mmu-mips.c | ||
| mmu-mips.h | ||
| system-mips.c | ||
| system-mips.h | ||