mirror of
https://github.com/Rockbox/rockbox.git
synced 2026-07-10 13:29:52 -04:00
e62ac0d2c6
add a plugin_ram_end symbol to plugin.lds and rewrite ovl_offset.pl to read plugin_ram_end and plugin_load_end_addr from the elf via nm. this removes all dependence on the linker map file format, which differs between gnu ld and lld. Change-Id: I66e623d9a2b44eb84ae7035155c84d8afe46df23
332 lines
9.8 KiB
Text
332 lines
9.8 KiB
Text
#define __ASSEMBLER__
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#include "config.h"
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#include "cpu.h"
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/* These output formats should be in the config-files */
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#ifdef CPU_COLDFIRE
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OUTPUT_FORMAT(elf32-m68k)
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#elif defined(CPU_ARM)
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OUTPUT_FORMAT(elf32-littlearm)
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#elif defined(CPU_MIPS)
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OUTPUT_FORMAT(elf32-littlemips)
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#else
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/* We can have an #error here we don't use this file when build sims! */
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#error Unknown CPU architecture
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#endif
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/* MCF5249 have 96KB of IRAM */
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#if CONFIG_CPU == MCF5249
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#define DRAMORIG 0x31000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#define IRAMORIG 0x1000c000
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#define IRAMSIZE 0xc000
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/* MCF5250 have 128KB of IRAM */
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#elif CONFIG_CPU == MCF5250
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#define DRAMORIG 0x31000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#define IRAMORIG 0x1000c800
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#define IRAMSIZE 0x13800
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#elif CONFIG_CPU == PP5022 || CONFIG_CPU == PP5024
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/* PP5022/24 have 128KB of IRAM */
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#define DRAMORIG 0x00000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#define IRAMORIG 0x4000c000
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#define IRAMSIZE 0x14000
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#elif defined(CPU_PP)
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/* all other PP's have 96KB of IRAM */
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#define DRAMORIG 0x00000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#define IRAMORIG 0x4000c000
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#define IRAMSIZE 0x0c000
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#elif CONFIG_CPU == IMX31L
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#define DRAMORIG 0x0
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#define DRAMSIZE ((MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE \
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- CODEC_SIZE - QHARRAY_SIZE - FRAME_SIZE - TTB_SIZE)
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#elif CONFIG_CPU == S3C2440
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#define DRAMORIG 0x0
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#define DRAMSIZE ((MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE \
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- CODEC_SIZE - LCD_BUFFER_SIZE - TTB_SIZE)
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#elif CONFIG_CPU==DM320
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#define DRAMORIG CONFIG_SDRAM_START
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE - LCD_TTB_AREA
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/* The bit of IRAM that is available is used in the core */
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#elif CONFIG_CPU==TCC7801
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#define DRAMORIG 0x20000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE - TTB_SIZE
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#define IRAMORIG 0x1000c000
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#define IRAMSIZE 0xc000
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#elif CONFIG_CPU==AS3525 && !defined(AMS_LOWMEM)
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#define DRAMORIG DRAM_ORIG
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#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - TTB_SIZE)
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#define IRAMORIG (IRAM_ORIG + 0x20000)
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#define IRAMSIZE (IRAM_ORIG + IRAM_SIZE - IRAMORIG)
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#elif CONFIG_CPU==AS3525v2 || (CONFIG_CPU == AS3525 && defined(AMS_LOWMEM))
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#define DRAMORIG DRAM_ORIG
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#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - TTB_SIZE)
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/* No IRAM defined, instead IRAM is exclusively used for the entire codec */
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#define CODEC_ORIGIN (IRAM_ORIG + IRAM_SIZE - CODEC_SIZE)
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#define PLUGIN_ORIGIN (DRAM_ORIG + DRAMSIZE)
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#elif CONFIG_CPU==S5L8700
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/* S5L8700 have 256KB of IRAM */
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#define DRAMORIG 0x08000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#define IRAMORIG (0x00000000 + (48*1024))
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#define IRAMSIZE (208*1024)
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#elif CONFIG_CPU==S5L8701
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/* S5L8701 have 176KB of IRAM */
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#define DRAMORIG 0x08000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#define IRAMORIG (0x00000000 + (48*1024))
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#define IRAMSIZE (128*1024)
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#elif CONFIG_CPU==S5L8702
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/* S5L8702 have 256KB of IRAM */
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/* IRAM1 (2nd 128KB block) is not used because it is slower than DRAM */
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#define DRAMORIG 0x08000000
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#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - TTB_SIZE)
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#define IRAMORIG (0x00000000 + (48*1024))
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#define IRAMSIZE (80*1024)
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#elif CONFIG_CPU==S5L8720
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/* S5L8720 have 192KB of IRAM */
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/* TODO: check if IRAM1 is also slow as in S5L8702 above */
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#define DRAMORIG 0x08000000
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#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - TTB_SIZE)
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#define IRAMORIG (0x00000000 + (56*1024))
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#define IRAMSIZE (136*1024)
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#elif CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
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/* fake 'iram' region occupies first 16k */
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#define DRAMORIG 0x80004000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE - 0x4000
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/* The bit of IRAM that is available is used in the core */
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#elif CONFIG_CPU == X1000
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#define DRAMORIG X1000_DRAM_BASE
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#define DRAMSIZE (X1000_DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE)
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#elif CONFIG_CPU == RK27XX
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#define DRAMORIG 0x60000000
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#elif CONFIG_CPU == IMX233
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/* The IRAM is too small and already partly used by the core */
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#define DRAMORIG CACHED_DRAM_ADDR
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#define DRAMSIZE (DRAM_SIZE - PLUGIN_BUFFER_SIZE - CODEC_SIZE - FRAME_SIZE - TTB_SIZE)
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#elif CONFIG_CPU == STM32H743
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#define DRAMORIG STM32_SDRAM1_BASE
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - CODEC_SIZE
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#else
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# error "DRAM/IRAM memory map not defined!"
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#endif
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#define PLUGIN_LENGTH PLUGIN_BUFFER_SIZE
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#ifndef CODEC_ORIGIN /* targets can specify another origin */
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#define CODEC_ORIGIN (DRAMORIG + (DRAMSIZE))
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#endif
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#ifndef PLUGIN_ORIGIN /* targets can specify another origin */
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#define PLUGIN_ORIGIN (CODEC_ORIGIN + CODEC_SIZE)
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#endif
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#ifdef CODEC
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#define THIS_LENGTH CODEC_SIZE
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#define THIS_ORIGIN CODEC_ORIGIN
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#elif defined OVERLAY_OFFSET
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#define THIS_LENGTH (DRAMSIZE - OVERLAY_OFFSET)
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#define THIS_ORIGIN (DRAMORIG + OVERLAY_OFFSET)
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#elif defined IMGVDECODER_OFFSET
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#define THIS_LENGTH (PLUGIN_LENGTH - IMGVDECODER_OFFSET)
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#define THIS_ORIGIN (PLUGIN_ORIGIN + IMGVDECODER_OFFSET)
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#else /* plugin */
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#define THIS_LENGTH PLUGIN_LENGTH
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#define THIS_ORIGIN PLUGIN_ORIGIN
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#endif
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#if defined(USE_IRAM) && (!defined(IRAMORIG) || !defined(IRAMSIZE))
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# error "USE_IRAM is set, but no IRAM region is defined!"
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#endif
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MEMORY
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{
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PLUGIN_RAM : ORIGIN = THIS_ORIGIN, LENGTH = THIS_LENGTH
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#if defined(USE_IRAM)
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PLUGIN_IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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#endif
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}
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SECTIONS
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{
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.header : {
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_plugin_start_addr = .;
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plugin_start_addr = .;
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KEEP(*(.header))
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} > PLUGIN_RAM
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.text :
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{
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*(.text*)
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#ifdef CPU_ARM
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*(.glue_7)
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*(.glue_7t)
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#endif
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} > PLUGIN_RAM
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.rodata :
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{
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*(.rodata*)
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} > PLUGIN_RAM
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.data :
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{
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*(.data*)
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} > PLUGIN_RAM
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#if defined(NOCACHE_BASE)
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/*
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* Allocate .ncdata based on the following constraints:
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*
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* 1. the LMA must be allocated at the next free LMA in
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* PLUGIN_RAM and aligned to a cacheline boundary.
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* 2. the VMA - LMA offset must equal NOCACHE_BASE.
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*/
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.ncdata ALIGN(. + NOCACHE_BASE, CACHEALIGN_SIZE) : ALIGN(CACHEALIGN_SIZE)
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{
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*(.ncdata*)
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. = ALIGN(CACHEALIGN_SIZE);
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} AT> PLUGIN_RAM
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#endif
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/DISCARD/ :
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{
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*(.eh_frame)
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#if !defined(USE_IRAM)
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.ibss)
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#endif
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#ifdef CPU_MIPS
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*(.MIPS.abiflags)
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*(.rel.dyn)
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#endif
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}
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.bss (NOLOAD) :
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{
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plugin_bss_start = .;
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_plugin_bss_start = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(0x4);
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} > PLUGIN_RAM
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#if defined(NOCACHE_BASE)
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/*
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* .ncbss has the same constraints as the .ncdata section
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* above but there is an extra complication: because it is
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* a NOLOAD section, unlike .ncdata it cannot consume any
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* VMAs or LMAs in PLUGIN_RAM itself.
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*
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* Because free VMA/LMAs in PLUGIN_RAM are unchanged, any
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* subsequent sections will get placed at the end of the
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* .bss section, overlapping .ncbss, which we don't want.
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*
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* One solution is to manually place the next sections to
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* account for the size of .ncbss, but a cleaner solution
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* is to define a dummy section (.ncbss_vma) allocated at
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* the same VMA as .ncbss and equal in size, and placed in
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* the PLUGIN_RAM region. This allocates the correct VMA
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* range in plugin RAM so that the next section will not
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* overlap .ncbss.
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*/
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.ncbss ALIGN(. + NOCACHE_BASE, CACHEALIGN_SIZE) (NOLOAD) : ALIGN(CACHEALIGN_SIZE)
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{
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*(.ncbss*)
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. = ALIGN(CACHEALIGN_SIZE);
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} AT> PLUGIN_RAM
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.ncbss_vma (NOLOAD) : ALIGN(CACHEALIGN_SIZE)
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{
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. += SIZEOF(.ncbss);
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} > PLUGIN_RAM
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#endif
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/* Final end of plugin after IRAM setup. The plugin or codec buffer
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is considered unused by the in-RAM image at this point once IRAM
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is copied. */
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.pluginend (NOLOAD) :
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{
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_plugin_end_addr = .;
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plugin_end_addr = .;
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} > PLUGIN_RAM
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#if defined(USE_IRAM)
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.iram IRAMORIG : AT(LOADADDR(.bss))
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{
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iramstart = .;
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*(.icode)
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*(.irodata)
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*(.idata)
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iramend = .;
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} > PLUGIN_IRAM
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iramcopy = LOADADDR(.iram);
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.ibss (NOLOAD) :
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{
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iedata = .;
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*(.ibss)
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. = ALIGN(0x4);
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iend = .;
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} > PLUGIN_IRAM
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loadendaddr = MAX(plugin_end_addr, LOADADDR(.iram) + SIZEOF(.iram));
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#else
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loadendaddr = plugin_end_addr;
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#endif
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/* This is for ovl_offset.pl and is the highest address that must
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be loaded into the plugin buffer (past the end of last data in
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stored image). */
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.pluginloadend loadendaddr :
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{
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_plugin_load_end_addr = .;
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plugin_load_end_addr = .;
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}
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_plugin_ram_end = ORIGIN(PLUGIN_RAM) + LENGTH(PLUGIN_RAM);
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plugin_ram_end = ORIGIN(PLUGIN_RAM) + LENGTH(PLUGIN_RAM);
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/* Special trick to avoid a linker error when no other sections are
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left after garbage collection (plugin not for this platform) */
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.comment 0 :
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{
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KEEP(*(.comment))
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}
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}
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#if defined(NOCACHE_BASE)
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/* Some asserts to make sure nocache sections appear correctly defined */
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ASSERT(LOADADDR(.ncdata) == ADDR(.ncdata) - NOCACHE_BASE, ".ncdata has incorrect LMA/VMA address");
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ASSERT(LOADADDR(.ncdata) % CACHEALIGN_SIZE == 0, ".ncdata incorrectly aligned");
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ASSERT(LOADADDR(.ncbss) == ADDR(.ncbss) - NOCACHE_BASE, ".ncbss has incorrect LMA/VMA address");
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ASSERT(LOADADDR(.ncbss) % CACHEALIGN_SIZE == 0, ".ncbss incorrectly aligned");
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ASSERT(ADDR(.ncbss_vma) == LOADADDR(.ncbss), ".ncbss_vma has wrong address");
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ASSERT(SIZEOF(.ncbss_vma) == SIZEOF(.ncbss), ".ncbss_vma has wrong size");
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#endif
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