mirror of
https://github.com/Rockbox/rockbox.git
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375a6bc9b1
This allows to reuse a register definition across similar SoCs that have the same layout of registers (same offsets), but are using a different base address for the peripheral. The include guard was also fixed to reflect the new file name of the header. Some registers were renamed in order to match the datasheet and for consistency with the other register numbering. Change-Id: I0192e227a3c467504b8fcd1eb684a7fc861f7896
150 lines
3.5 KiB
C
150 lines
3.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include "config.h"
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#include "cpu.h"
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#include "system.h"
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#include "s5l87xx.h"
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#include "uc87xx.h"
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/*
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* s5l8702 UC87XX HW: 1 UARTC, 4 ports
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*/
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static struct uartc_port *uartc_port_l[UARTC_N_PORTS];
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const struct uartc s5l8702_uartc =
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{
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.id = 0,
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.baddr = UARTC_BASE_ADDR,
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.port_off = UARTC_PORT_OFFSET,
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.n_ports = UARTC_N_PORTS,
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.port_l = uartc_port_l,
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};
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/*
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* Device level functions specific to S5L8702
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*/
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void uart_target_enable_gpio(int uart_id, int port_id)
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{
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(void) uart_id;
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switch (port_id) {
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case 0:
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/* configure UART0 Tx/Rx GPIO ports */
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PCON0 = (PCON0 & 0xff00ffff) | 0x00220000;
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break;
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case 1:
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/* configure UART1 GPIO ports, including RTS/CTS signals */
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PCON13 = (PCON13 & 0xff0000ff) | 0x00222200;
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break;
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case 2:
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case 3:
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/* unknown */
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default:
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break;
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}
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}
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void uart_target_disable_gpio(int uart_id, int port_id)
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{
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(void) uart_id;
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switch (port_id) {
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/* configure minimal power consumption */
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case 0:
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PCON0 = (PCON0 & 0xff00ffff) | 0x00ee0000;
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break;
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case 1:
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PCON13 = (PCON13 & 0xff0000ff) | 0x00eeee00;
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break;
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case 2:
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case 3:
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default:
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break;
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}
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}
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void uart_target_enable_irq(int uart_id, int port_id)
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{
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(void) uart_id;
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VIC0INTENABLE = 1 << IRQ_UART(port_id);
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}
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void uart_target_disable_irq(int uart_id, int port_id)
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{
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(void) uart_id;
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VIC0INTENCLEAR = 1 << IRQ_UART(port_id);
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}
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void uart_target_clear_irq(int uart_id, int port_id)
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{
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(void) uart_id;
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(void) port_id;
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}
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void uart_target_enable_clocks(int uart_id)
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{
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(void) uart_id;
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PWRCON(1) &= ~(1 << (CLOCKGATE_UARTC - 32));
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}
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void uart_target_disable_clocks(int uart_id)
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{
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(void) uart_id;
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PWRCON(1) |= (1 << (CLOCKGATE_UARTC - 32));
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}
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/*
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* ISRs
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*/
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/* On Classic, PORT0 interrupts are not used when iAP is disabled */
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#if !defined(IPOD_6G) || defined(IPOD_ACCESSORY_PROTOCOL)
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void ICODE_ATTR INT_UART0(void)
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{
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uartc_callback(&s5l8702_uartc, 0);
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}
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#endif
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/* PORT1,2,3 not used on Classic */
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#ifndef IPOD_6G
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void ICODE_ATTR INT_UART1(void)
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{
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uartc_callback(&s5l8702_uartc, 1);
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}
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void ICODE_ATTR INT_UART2(void)
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{
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uartc_callback(&s5l8702_uartc, 2);
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}
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void ICODE_ATTR INT_UART3(void)
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{
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uartc_callback(&s5l8702_uartc, 3);
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}
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#endif
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/* Main init */
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void uart_init(void)
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{
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uartc_open(&s5l8702_uartc);
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}
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