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cbace906c6
The filesystem API often passes in unaligned receive buffers, and some code (eg BMP reader) processes data in-place, leading to data loss when we dropped the cache. (And document exactly what we're doing, so we don't go through this again at $future_date) Change-Id: If47a7f2148a5a1a43777f0bd3be1bdfe8239e91e
273 lines
8.4 KiB
C
273 lines
8.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2009 by Maurus Cuelenaere
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* Copyright (C) 2015 by Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "mips.h"
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#include "mipsregs.h"
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#include "system.h"
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#include "mmu-mips.h"
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#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
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/* XBurst core has 32 JTLB entries */
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#define NR_TLB_ENTRIES 32
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#else
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#error please define NR_TLB_ENTRIES
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#endif
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#define BARRIER \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" ssnop \n" \
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" ssnop \n" \
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" ssnop \n" \
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" ssnop \n" \
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" ssnop \n" \
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" ssnop \n" \
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" .set pop \n");
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#define DEFAULT_PAGE_SHIFT PL_4K
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#define DEFAULT_PAGE_MASK PM_4K
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#define UNIQUE_ENTRYHI(idx, ps) (A_K0BASE + ((idx) << (ps + 1)))
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#define ASID_MASK M_EntryHiASID
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#define VPN2_SHIFT S_EntryHiVPN2
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#define PFN_SHIFT S_EntryLoPFN
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#define PFN_MASK 0xffffff
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static void local_flush_tlb_all(void)
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{
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unsigned long old_ctx;
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int entry;
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unsigned int old_irq = disable_irq_save();
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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BARRIER;
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/* blast all entries except the wired one */
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for(entry = read_c0_wired(); entry < NR_TLB_ENTRIES; entry++)
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{
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/* Make sure all entries differ and are in unmapped space, making them
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* impossible to match */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry, DEFAULT_PAGE_SHIFT));
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write_c0_index(entry);
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BARRIER;
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tlb_write_indexed();
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}
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BARRIER;
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write_c0_entryhi(old_ctx);
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restore_irq(old_irq);
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}
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static void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask)
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{
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unsigned long wired;
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unsigned long old_pagemask;
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unsigned long old_ctx;
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unsigned int old_irq = disable_irq_save();
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old_ctx = read_c0_entryhi() & ASID_MASK;
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old_pagemask = read_c0_pagemask();
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wired = read_c0_wired();
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write_c0_wired(wired + 1);
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write_c0_index(wired);
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BARRIER;
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write_c0_pagemask(pagemask);
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write_c0_entryhi(entryhi);
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write_c0_entrylo0(entrylo0);
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write_c0_entrylo1(entrylo1);
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BARRIER;
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tlb_write_indexed();
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BARRIER;
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write_c0_entryhi(old_ctx);
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BARRIER;
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write_c0_pagemask(old_pagemask);
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local_flush_tlb_all();
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restore_irq(old_irq);
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}
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void map_address(unsigned long virtual, unsigned long physical,
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unsigned long length, unsigned int cache_flags)
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{
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unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT;
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unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT;
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unsigned long entryhi = virtual & ~VPN2_SHIFT;
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entry0 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) );
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entry1 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) );
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add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK);
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}
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void mmu_init(void)
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{
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write_c0_pagemask(DEFAULT_PAGE_MASK);
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write_c0_wired(0);
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write_c0_framemask(0);
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local_flush_tlb_all();
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}
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/* Target specific operations:
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* - invalidate BTB (Branch Table Buffer)
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* - sync barrier after cache operations */
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#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
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#define INVALIDATE_BTB() \
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do { \
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register unsigned long tmp; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips32 \n" \
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" mfc0 %0, $16, 7 \n" \
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" ssnop \n" \
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" ori %0, 2 \n" \
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" mtc0 %0, $16, 7 \n" \
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" ssnop \n" \
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" .set pop \n" \
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: "=&r"(tmp)); \
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} while (0)
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#define SYNC_WB() __asm__ __volatile__ ("sync":::"memory")
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#else /* !JZ4732 */
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#define INVALIDATE_BTB() do { } while(0)
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#define SYNC_WB() do { } while(0)
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#endif /* CONFIG_CPU */
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#define __CACHE_OP(op, addr) \
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__asm__ __volatile__( \
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" .set push\n\t \n" \
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" .set noreorder \n" \
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" .set mips32\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "m"(*(unsigned char *)(addr)))
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/* rockbox cache api */
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/* Writeback whole D-cache
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* Alias to commit_discard_dcache() as there is no index type
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* variant of writeback-only operation
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*/
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void commit_dcache(void) __attribute__((alias("commit_discard_dcache")));
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/* Writeback whole D-cache and invalidate D-cache lines */
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void commit_discard_dcache(void)
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{
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register unsigned int i;
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/* Use index type operation and iterate whole cache */
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for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE)
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__CACHE_OP(DCIndexWBInv, i);
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SYNC_WB();
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}
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/* Writeback lines of D-cache corresponding to address range and
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* invalidate those D-cache lines
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*/
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void commit_discard_dcache_range(const void *base, unsigned int size)
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{
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char *ptr = CACHEALIGN_DOWN((char*)base);
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char *end = CACHEALIGN_UP((char*)base + size);
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for(; ptr != end; ptr += CACHEALIGN_SIZE)
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__CACHE_OP(DCHitWBInv, ptr);
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SYNC_WB();
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}
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/* Writeback lines of D-cache corresponding to address range
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*/
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void commit_dcache_range(const void *base, unsigned int size)
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{
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char *ptr = CACHEALIGN_DOWN((char*)base);
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char *end = CACHEALIGN_UP((char*)base + size);
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for(; ptr != end; ptr += CACHEALIGN_SIZE)
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__CACHE_OP(DCHitWB, ptr);
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SYNC_WB();
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}
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/* Invalidate D-cache lines corresponding to address range
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* WITHOUT writeback
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*/
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void discard_dcache_range(const void *base, unsigned int size)
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{
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char *ptr = CACHEALIGN_DOWN((char*)base);
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char *end = CACHEALIGN_UP((char*)base + size);
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/* If the start of the buffer is unaligned, write
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back that cacheline and shrink up the region
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to discard. */
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if (base != ptr) {
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__CACHE_OP(DCHitWBInv, ptr);
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ptr += CACHEALIGN_SIZE;
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}
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/* If the end of the buffer is unaligned, write back that
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cacheline and shrink down the region to discard. */
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if (ptr != end && (end !=((char*)base + size))) {
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end -= CACHEALIGN_SIZE;
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__CACHE_OP(DCHitWBInv, ptr);
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}
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/* Finally, discard whatever is left */
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for(; ptr != end; ptr += CACHEALIGN_SIZE)
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__CACHE_OP(DCHitInv, ptr);
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SYNC_WB();
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}
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/* Invalidate whole I-cache */
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static void discard_icache(void)
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{
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register unsigned int i;
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asm volatile (".set push \n"
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".set noreorder \n"
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".set mips32 \n"
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"mtc0 $0, $28 \n" /* TagLo */
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"mtc0 $0, $29 \n" /* TagHi */
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".set pop \n"
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);
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/* Use index type operation and iterate whole cache */
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for (i=A_K0BASE; i<A_K0BASE+CACHE_SIZE; i+=CACHEALIGN_SIZE)
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__CACHE_OP(ICIndexStTag, i);
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INVALIDATE_BTB();
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}
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/* Invalidate the entire I-cache
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* and writeback + invalidate the entire D-cache
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*/
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void commit_discard_idcache(void)
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{
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commit_discard_dcache();
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discard_icache();
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}
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