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3ed9fb3115
M-profile cores manage interrupts differently from classic cores and lack the FIQ. Split the interrupt management parts out into separate headers but keep the endian swapping routines (which are not profile-dependent) in the common system-arm header. The initial part of the vector table is common to all Cortex-M CPUs and is intended to be included by the target linker script, with the vendor-specific part of the vector table appended to it. Change-Id: Ib2ad5b9dc41db27940e39033cfef4308923db66d
99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 by Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_ARM_MICRO_H
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#define SYSTEM_ARM_MICRO_H
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#define IRQ_ENABLED 0x00
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#define IRQ_DISABLED 0x01
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#define IRQ_STATUS 0x01
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#define HIGHEST_IRQ_LEVEL IRQ_DISABLED
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#define disable_irq_save() \
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set_irq_level(IRQ_DISABLED)
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/* For compatibility with ARM classic */
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#define CPU_MODE_THREAD_CONTEXT 0
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#define is_thread_context() \
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(get_interrupt_number() == CPU_MODE_THREAD_CONTEXT)
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/* Assert that the processor is in the desired execution mode
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* mode: Processor mode value to test for
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* rstatus...: Ignored; for compatibility with ARM classic only.
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*/
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#define ASSERT_CPU_MODE(mode, rstatus...) \
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({ unsigned long __massert = (mode); \
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unsigned long __mproc = get_interrupt_number(); \
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if (__mproc != __massert) \
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panicf("Incorrect CPU mode in %s (0x%02lx!=0x%02lx)", \
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__func__, __mproc, __massert); })
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/* Core-level interrupt masking */
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static inline int set_irq_level(int primask)
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{
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int oldvalue;
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asm volatile ("mrs %0, primask\n"
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"msr primask, %1\n"
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: "=r"(oldvalue) : "r"(primask));
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return oldvalue;
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}
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static inline void restore_irq(int primask)
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{
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asm volatile ("msr primask, %0" :: "r"(primask));
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}
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static inline void enable_irq(void)
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{
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asm volatile ("cpsie i");
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}
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static inline void disable_irq(void)
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{
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asm volatile ("cpsid i");
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}
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static inline bool irq_enabled(void)
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{
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int primask;
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asm volatile ("mrs %0, primask" : "=r"(primask));
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return !(primask & 1);
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}
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static inline unsigned long get_interrupt_number(void)
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{
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unsigned long ipsr;
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asm volatile ("mrs %0, ipsr" : "=r"(ipsr));
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return ipsr & 0x1ff;
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}
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static inline void core_sleep(void)
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{
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asm volatile ("wfi");
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enable_irq();
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}
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#endif /* SYSTEM_ARM_MICRO_H */
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