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3ed9fb3115
M-profile cores manage interrupts differently from classic cores and lack the FIQ. Split the interrupt management parts out into separate headers but keep the endian swapping routines (which are not profile-dependent) in the common system-arm header. The initial part of the vector table is common to all Cortex-M CPUs and is intended to be included by the target linker script, with the vendor-specific part of the vector table appended to it. Change-Id: Ib2ad5b9dc41db27940e39033cfef4308923db66d
280 lines
8 KiB
C
280 lines
8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_ARM_CLASSIC_H
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#define SYSTEM_ARM_CLASSIC_H
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#define IRQ_ENABLED 0x00
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#define IRQ_DISABLED 0x80
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#define IRQ_STATUS 0x80
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#define FIQ_ENABLED 0x00
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#define FIQ_DISABLED 0x40
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#define FIQ_STATUS 0x40
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#define IRQ_FIQ_ENABLED 0x00
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#define IRQ_FIQ_DISABLED 0xc0
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#define IRQ_FIQ_STATUS 0xc0
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#define HIGHEST_IRQ_LEVEL IRQ_DISABLED
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#define set_irq_level(status) \
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set_interrupt_status((status), IRQ_STATUS)
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#define set_fiq_status(status) \
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set_interrupt_status((status), FIQ_STATUS)
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#define disable_irq_save() \
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disable_interrupt_save(IRQ_STATUS)
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#define disable_fiq_save() \
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disable_interrupt_save(FIQ_STATUS)
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#define restore_irq(cpsr) \
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restore_interrupt(cpsr)
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#define restore_fiq(cpsr) \
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restore_interrupt(cpsr)
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#define disable_irq() \
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disable_interrupt(IRQ_STATUS)
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#define enable_irq() \
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enable_interrupt(IRQ_STATUS)
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#define disable_fiq() \
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disable_interrupt(FIQ_STATUS)
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#define enable_fiq() \
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enable_interrupt(FIQ_STATUS)
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#define irq_enabled() \
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interrupt_enabled(IRQ_STATUS)
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#define fiq_enabled() \
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interrupt_enabled(FIQ_STATUS)
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#define ints_enabled() \
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interrupt_enabled(IRQ_FIQ_STATUS)
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#define irq_enabled_checkval(val) \
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(((val) & IRQ_STATUS) == 0)
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#define fiq_enabled_checkval(val) \
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(((val) & FIQ_STATUS) == 0)
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#define ints_enabled_checkval(val) \
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(((val) & IRQ_FIQ_STATUS) == 0)
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#define CPU_MODE_USER 0x10
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#define CPU_MODE_FIQ 0x11
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#define CPU_MODE_IRQ 0x12
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#define CPU_MODE_SVC 0x13
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#define CPU_MODE_ABT 0x17
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#define CPU_MODE_UNDEF 0x1b
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#define CPU_MODE_SYS 0x1f
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/* We run in SYS mode */
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#define CPU_MODE_THREAD_CONTEXT CPU_MODE_SYS
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#define is_thread_context() \
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(get_processor_mode() == CPU_MODE_THREAD_CONTEXT)
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/* Assert that the processor is in the desired execution mode
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* mode: Processor mode value to test for
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* rstatus...: Provide if you already have the value saved, otherwise leave
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* blank to get it automatically.
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*/
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#define ASSERT_CPU_MODE(mode, rstatus...) \
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({ unsigned long __massert = (mode); \
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unsigned long __mproc = *#rstatus ? \
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((rstatus +0) & 0x1f) : get_processor_mode(); \
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if (__mproc != __massert) \
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panicf("Incorrect CPU mode in %s (0x%02lx!=0x%02lx)", \
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__func__, __mproc, __massert); })
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/* Core-level interrupt masking */
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static inline int set_interrupt_status(int status, int mask)
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{
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unsigned long cpsr;
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int oldstatus;
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/* Read the old levels and set the new ones */
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#if (defined(CREATIVE_ZVM) || defined(CREATIVE_ZV)) && defined(BOOTLOADER)
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// FIXME: This workaround is for a problem with inlining;
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// for some reason 'mask' gets treated as a variable/non-immediate constant
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// but only on this build. All others (including the nearly-identical mrobe500boot) are fine
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asm volatile (
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"mrs %1, cpsr \n"
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"bic %0, %1, %[mask] \n"
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"orr %0, %0, %2 \n"
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"msr cpsr_c, %0 \n"
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: "=&r,r"(cpsr), "=&r,r"(oldstatus)
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: "r,i"(status & mask), [mask]"r,i"(mask));
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#else
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asm volatile (
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"mrs %1, cpsr \n"
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"bic %0, %1, %[mask] \n"
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"orr %0, %0, %2 \n"
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"msr cpsr_c, %0 \n"
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: "=&r,r"(cpsr), "=&r,r"(oldstatus)
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: "r,i"(status & mask), [mask]"i,i"(mask));
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#endif
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return oldstatus;
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}
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static inline void restore_interrupt(int cpsr)
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{
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/* Set cpsr_c from value returned by disable_interrupt_save
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* or set_interrupt_status */
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asm volatile ("msr cpsr_c, %0" : : "r"(cpsr));
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}
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static inline bool interrupt_enabled(int status)
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{
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unsigned long cpsr;
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asm ("mrs %0, cpsr" : "=r"(cpsr));
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return (cpsr & status) == 0;
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}
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static inline unsigned long get_processor_mode(void)
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{
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unsigned long cpsr;
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asm ("mrs %0, cpsr" : "=r"(cpsr));
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return cpsr & 0x1f;
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}
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/* ARM_ARCH version section for architecture*/
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#if ARM_ARCH >= 6
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static inline void enable_interrupt(int mask)
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{
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/* Clear I and/or F disable bit */
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/* mask is expected to be constant and so only relevent branch
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* is preserved */
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switch (mask & IRQ_FIQ_STATUS)
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{
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case IRQ_STATUS:
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asm volatile ("cpsie i");
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break;
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case FIQ_STATUS:
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asm volatile ("cpsie f");
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break;
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case IRQ_FIQ_STATUS:
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asm volatile ("cpsie if");
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break;
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}
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}
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static inline void disable_interrupt(int mask)
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{
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/* Set I and/or F disable bit */
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/* mask is expected to be constant and so only relevent branch
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* is preserved */
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switch (mask & IRQ_FIQ_STATUS)
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{
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case IRQ_STATUS:
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asm volatile ("cpsid i");
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break;
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case FIQ_STATUS:
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asm volatile ("cpsid f");
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break;
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case IRQ_FIQ_STATUS:
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asm volatile ("cpsid if");
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break;
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}
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}
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static inline int disable_interrupt_save(int mask)
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{
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/* Set I and/or F disable bit and return old cpsr value */
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int cpsr;
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/* mask is expected to be constant and so only relevent branch
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* is preserved */
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asm volatile("mrs %0, cpsr" : "=r"(cpsr));
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switch (mask & IRQ_FIQ_STATUS)
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{
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case IRQ_STATUS:
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asm volatile ("cpsid i");
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break;
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case FIQ_STATUS:
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asm volatile ("cpsid f");
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break;
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case IRQ_FIQ_STATUS:
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asm volatile ("cpsid if");
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break;
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}
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return cpsr;
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}
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#else /* ARM_ARCH < 6 */
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static inline void enable_interrupt(int mask)
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{
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/* Clear I and/or F disable bit */
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int tmp;
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asm volatile (
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"mrs %0, cpsr \n"
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"bic %0, %0, %1 \n"
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"msr cpsr_c, %0 \n"
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: "=&r"(tmp) : "i"(mask));
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}
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static inline void disable_interrupt(int mask)
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{
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/* Set I and/or F disable bit */
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int tmp;
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asm volatile (
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"mrs %0, cpsr \n"
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"orr %0, %0, %1 \n"
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"msr cpsr_c, %0 \n"
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: "=&r"(tmp) : "i"(mask));
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}
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static inline int disable_interrupt_save(int mask)
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{
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/* Set I and/or F disable bit and return old cpsr value */
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int cpsr, tmp;
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asm volatile (
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"mrs %1, cpsr \n"
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"orr %0, %1, %2 \n"
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"msr cpsr_c, %0 \n"
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: "=&r"(tmp), "=&r"(cpsr)
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: "i"(mask));
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return cpsr;
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}
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#endif /* ARM_ARCH */
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#if defined(CPU_TCC780X) /* Single core only for now */ \
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|| CONFIG_CPU == IMX31L || CONFIG_CPU == DM320 || CONFIG_CPU == AS3525 \
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|| CONFIG_CPU == S3C2440 || CONFIG_CPU == S5L8701 || CONFIG_CPU == AS3525v2 \
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|| CONFIG_CPU == S5L8702 || CONFIG_CPU == S5L8720
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/* Use the generic ARMv4/v5/v6 wait for IRQ */
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static inline void core_sleep(void)
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{
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asm volatile (
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"mcr p15, 0, %0, c7, c0, 4 \n" /* Wait for interrupt */
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#if CONFIG_CPU == IMX31L
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"nop\n nop\n nop\n nop\n nop\n" /* Clean out the pipes */
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#endif
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: : "r"(0)
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);
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enable_irq();
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}
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#else
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/* Skip this if special code is required and implemented */
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#if !(defined(CPU_PP)) && CONFIG_CPU != RK27XX && CONFIG_CPU != IMX233
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static inline void core_sleep(void)
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{
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/* TODO: core_sleep not implemented, battery life will be decreased */
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enable_irq();
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}
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#endif /* CPU_PP */
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#endif
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#endif /* SYSTEM_ARM_CLASSIC_H */
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