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c249dea2b7
GAS warns about unpredictable behavior of "ldr sp, [a1], #4" that exists on Cortex-M3 (errata 752419) but this warning is incorrectly issued on other cores too (eg, Cortex-M7). Since the fix is just one extra instruction we may as well apply the workaround for all Cortex-M targets. Change-Id: I0c2aa46837f776d67d0236b627af1572aa5ab307
185 lines
5.2 KiB
ArmAsm
185 lines
5.2 KiB
ArmAsm
/* This is a simple version of setjmp and longjmp.
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Nick Clifton, Cygnus Solutions, 13 June 1997. */
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/* ANSI concatenation macros. */
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#define CONCAT(a, b) CONCAT2(a, b)
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#define CONCAT2(a, b) a##b
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#ifndef __USER_LABEL_PREFIX__
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#error __USER_LABEL_PREFIX__ not defined
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#endif
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#define SYM(x) CONCAT (__USER_LABEL_PREFIX__, x)
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#ifdef __ELF__
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#define TYPE(x) .type SYM(x),function
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#define SIZE(x) .size SYM(x), . - SYM(x)
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#else
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#define TYPE(x)
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#define SIZE(x)
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#endif
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/* Arm/Thumb interworking support:
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The interworking scheme expects functions to use a BX instruction
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to return control to their parent. Since we need this code to work
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in both interworked and non-interworked environments as well as with
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older processors which do not have the BX instruction we do the
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following:
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Test the return address.
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If the bottom bit is clear perform an "old style" function exit.
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(We know that we are in ARM mode and returning to an ARM mode caller).
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Otherwise use the BX instruction to perform the function exit.
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We know that we will never attempt to perform the BX instruction on
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an older processor, because that kind of processor will never be
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interworked, and a return address with the bottom bit set will never
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be generated.
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In addition, we do not actually assemble the BX instruction as this would
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require us to tell the assembler that the processor is an ARM7TDMI and
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it would store this information in the binary. We want this binary to be
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able to be linked with binaries compiled for older processors however, so
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we do not want such information stored there.
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If we are running using the APCS-26 convention however, then we never
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test the bottom bit, because this is part of the processor status.
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Instead we just do a normal return, since we know that we cannot be
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returning to a Thumb caller - the Thumb does not support APCS-26.
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Function entry is much simpler. If we are compiling for the Thumb we
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just switch into ARM mode and then drop through into the rest of the
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function. The function exit code will take care of the restore to
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Thumb mode.
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For Thumb-2 do everything in Thumb mode. */
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#ifdef __APCS_26__
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#define RET movs pc, lr
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#elif defined(__thumb2__)
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#define RET bx lr
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#elif !defined(ROCKBOX_SUPPORTS_AN_ARMV4_NON_T_CPU)
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#define RET bx lr /* BX exists on v4T, v5 and more recent architectures */
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#else
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#define RET tst lr, #1; \
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moveq pc, lr ; \
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.word 0xe12fff1e /* bx lr */
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#endif
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#ifdef __thumb2__
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.macro COND where when
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i\where \when
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.endm
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#else
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.macro COND where when
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.endm
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#endif
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#if defined(__thumb2__)
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.syntax unified
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.macro MODE
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.thumb
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.thumb_func
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.endm
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.macro PROLOGUE name
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.endm
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#elif defined(__thumb__)
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#define MODE .thumb_func
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.macro PROLOGUE name
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.code 16
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bx pc
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nop
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.code 32
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SYM (.arm_start_of.\name):
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.endm
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#else /* Arm */
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#define MODE .code 32
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.macro PROLOGUE name
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.endm
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#endif
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.macro FUNC_START name
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.text
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.align 2
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MODE
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.globl SYM (\name)
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TYPE (\name)
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SYM (\name):
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PROLOGUE \name
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.endm
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.macro FUNC_END name
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RET
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SIZE (\name)
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.endm
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/* --------------------------------------------------------------------
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int setjmp (jmp_buf);
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-------------------------------------------------------------------- */
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FUNC_START setjmp
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/* Save all the callee-preserved registers into the jump buffer. */
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#ifdef __thumb2__
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stmea a1!, { v1-v7, fp, ip, lr }
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str sp, [a1],#+4
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#else
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stmea a1!, { v1-v7, fp, ip, sp, lr }
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#endif
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#if 0 /* Simulator does not cope with FP instructions yet. */
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#ifndef __SOFTFP__
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/* Save the floating point registers. */
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sfmea f4, 4, [a1]
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#endif
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#endif
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/* When setting up the jump buffer return 0. */
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mov a1, #0
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FUNC_END setjmp
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/* --------------------------------------------------------------------
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volatile void longjmp (jmp_buf, int);
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-------------------------------------------------------------------- */
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FUNC_START longjmp
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/* If we have stack extension code it ought to be handled here. */
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/* Restore the registers, retrieving the state when setjmp() was called. */
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#ifdef __thumb2__
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ldmfd a1!, { v1-v7, fp, ip, lr }
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#if __ARM_ARCH_PROFILE == 'M'
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/*
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* Errata 752419: Interrupted loads to SP can cause erroneous behaviour
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* Apply the suggested workaround of loading to an intermediate register
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* and then moving into sp. This only affects Cortex-M3 but a warning is
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* issued by the assembler for all armv7-m targets with binutils 2.38.
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*/
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ldr a3, [a1], #4
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mov sp, a3
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#else
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ldr sp, [a1], #4
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#endif
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#else
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ldmfd a1!, { v1-v7, fp, ip, sp, lr }
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#endif
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#if 0 /* Simulator does not cope with FP instructions yet. */
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#ifndef __SOFTFP__
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/* Restore floating point registers as well. */
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lfmfd f4, 4, [a1]
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#endif
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#endif
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/* Put the return value into the integer result register.
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But if it is zero then return 1 instead. */
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movs a1, a2
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#ifdef __thumb2__
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it eq
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#endif
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moveq a1, #1
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FUNC_END longjmp
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