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bbe72761a4
Some purely mechanical fixes to get the normal build working. Besides missing symbols all the plugins and codecs build just fine. Change-Id: I946ba39096a46be8308450bafd51a0995db8e323
615 lines
18 KiB
C
615 lines
18 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: lcd-nano2g.c 28868 2010-12-21 06:59:17Z Buschel $
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*
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* Copyright (C) 2009 by Dave Chapman
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "config.h"
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#include "kernel.h"
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#include "system.h"
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#include "cpu.h"
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#include "lcd.h"
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#ifdef IPOD_6G
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#include "pmu-target.h"
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#endif
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#include "backlight-target.h"
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#include "s5l87xx.h"
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#include "clocking-s5l8702.h"
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#include "dma-s5l8702.h"
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#include "lcd-s5l8702.h"
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#include "lcd-target.h"
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// TODO TODO TODO: HAVE_LCD_ENABLE
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/* Switch command/frame mode:
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*
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* XXX: WIP, TBC
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*
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* Configures MPU interface and pixel mode.
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*
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* Frame mode:
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* 6g:
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* 16-bit 8080-series parallel MPU interface
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* pixel mode: RBG565/1-transfer
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* APB[15:0] -> D[17:10,8:1]
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* nano3g:
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* 9-bit 8080-series parallel PMU interface (TBC)
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* pixel mode: RGB565/2-transfers (TBC)
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* APB[15:0] -> D[8:1] + D[8:1] (TBC)
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*
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* Command mode:
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* LCD HW that uses 8-bit command set (6g, nano3g):
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* 8-bit 8080-series parallel MPU interface
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* APB[7:0] -> D[8:1]
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* LCD HW that uses 16-bit command set (6g):
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* 18-bit 8080-series parallel MPU interface (TBC)
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* APB[15:0] -> D[17:10,8:1]
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*
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* See ILI9320, ILI9326, ILI9340 DS.
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*/
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/* XXX: see ili9340, pg.27 for MCU interface selection,
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* bit31 could be the one that selects interface D[7:0] or D[8:1] for 8-bit), Type-I uses D[7:0] and Type-II uses D[17:10] (ILI9340)
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* 9-bit D[8:0] D[17:9]
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* 16-bit D[15:0] D[17:10],D[8:1]
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* 18-bit D[17:0] D[17:0]
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* bit24 could be the one that selects interface D[8:1] or D[17:10]
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* MCU_interface Mode Pins Write Read
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* #define LCD_MODE_8 0x80000c20 8080 MCU 8-bit bus iface D[8:1] APB[7:0] -> D[8:1] D[8:1] -> LCD_DBUFF[8:1]
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* #define LCD_MODE_9 0x81100db8 9-bit
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* #define LCD_MODE_16 0x80100db0 16-bit D[17:10,8:1] APB[15:0] -> D[17:10,8:1]
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* #define LCD_MODE_18 0x80000da8 18-bit D[17:0] APB[17:0] -> D[17:0] (TBC)
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*
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* #define LCD_MODE_8 0x80000c20 // LCD_MODE_P8T1 // paralled 8-bit, 1 transfer, TBC: DB[17:10] or DB[8:1] ???
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* #define LCD_MODE_9 0x81100db8 // LCD_MODE_P9T2 // TBC: DB[8:1] or DB[17:10] ???, 2-transfers or 1.5-transfers, RGB565 or RBG666 ???
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* #define LCD_MODE_16 0x80100db0 // LCD_MODE_P16T1 // TBC: DB[17:10,8:1]
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* #define LCD_MODE_18 0x80000da8 // LCD_MODE_P18T1 // TBC: DB[17:10,8:1]
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*/
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#define LCD_MODE_P8 0x80000c20 // LCD_MODE_P8T1 // paralled 8-bit, 1 transfer, TBC: DB[17:10] or DB[8:1] ???
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#define LCD_MODE_P8b 0x80100c20 // TODO: see if it influences, so far we are using it in nano3g with 0x80000c20 and it seems to be working fine
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// It may be a "pixel format" setting for 8 bit, which would only affect DATA and not CMD ???
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#define LCD_MODE_P9 0x81100db8 // LCD_MODE_P9T2 // TBC: DB[8:1] or DB[17:10] ???, 2-transfers or 1.5-transfers, RGB565 or RBG666 ???
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#define LCD_MODE_P16 0x80100db0 // LCD_MODE_P16T1 // TBC: DB[17:10,8:1]
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#define LCD_MODE_P18 0x80000da8 // LCD_MODE_P18T1 // TBC: DB[17:10,8:1]
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#define LCD_MODE_S8 0x41000c20 // nano4g
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#define LCD_MODE_S9 0x41100db8 // nano4g
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#ifdef S5L_LCD_WITH_CMDSET16
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/* LCD type 16-bit register defines */
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#define R_HORIZ_GRAM_ADDR_SET 0x200
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#define R_VERT_GRAM_ADDR_SET 0x201
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#define R_WRITE_DATA_TO_GRAM 0x202
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#define R_HORIZ_ADDR_START_POS 0x210
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#define R_HORIZ_ADDR_END_POS 0x211
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#define R_VERT_ADDR_START_POS 0x212
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#define R_VERT_ADDR_END_POS 0x213
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#endif
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/* LCD type 8-bit register defines */
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#define R_COLUMN_ADDR_SET 0x2a
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#define R_ROW_ADDR_SET 0x2b
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#define R_MEMORY_WRITE 0x2c
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/** globals **/
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int lcd_type; /* also needed in debug-s5l8702.c */
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static struct mutex lcd_mutex;
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static uint16_t lcd_dblbuf[LCD_HEIGHT][LCD_WIDTH] CACHEALIGN_ATTR;
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static bool lcd_ispowered;
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/* TODO: there is no info about these specific drivers,
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some useful info on similar HW such as ILI9320, ILI9326, ILI9340 and */
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static struct lcd_info_rec *lcd_info;
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static void (*lcd_run_seq)(void*);
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/* LCD_CONFIG values for command/frame modes */
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static uint32_t lcd_cmd_mode IDATA_ATTR;
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static uint32_t lcd_frame_mode IDATA_ATTR;
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// TODO
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/* Each target must define a list containing all supported LCD types */
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// extern struct lcd_info_rec lcd_info_list[];
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// static struct lcd_info_rec lcd_info_list[];
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/* DMA configuration */
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/* One single transfer at once, needed LLIs:
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* screen_size / (DMAC_LLI_MAX_COUNT << swidth) =
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* (320*240*2) / (4095*2) = 19
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*/
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#define LCD_DMA_TSKBUF_SZ 1 /* N tasks, MUST be pow2 */
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#define LCD_DMA_LLIBUF_SZ 32 /* N LLIs, MUST be pow2 */
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static struct dmac_tsk lcd_dma_tskbuf[LCD_DMA_TSKBUF_SZ];
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static struct dmac_lli volatile \
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lcd_dma_llibuf[LCD_DMA_LLIBUF_SZ] CACHEALIGN_ATTR;
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static struct dmac_ch lcd_dma_ch =
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{
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.dmac = &s5l8702_dmac0,
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.prio = DMAC_CH_PRIO(4),
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.cb_fn = NULL,
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.tskbuf = lcd_dma_tskbuf,
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.tskbuf_mask = LCD_DMA_TSKBUF_SZ - 1,
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.queue_mode = QUEUE_NORMAL,
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.llibuf = lcd_dma_llibuf,
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.llibuf_mask = LCD_DMA_LLIBUF_SZ - 1,
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.llibuf_bus = DMAC_MASTER_AHB1,
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};
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static struct dmac_ch_cfg lcd_dma_ch_cfg =
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{
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.srcperi = S5L8702_DMAC0_PERI_MEM,
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.dstperi = S5L8702_DMAC0_PERI_LCD_WR,
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.sbsize = DMACCxCONTROL_BSIZE_1,
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.dbsize = DMACCxCONTROL_BSIZE_1,
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.swidth = DMACCxCONTROL_WIDTH_16,
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.dwidth = DMACCxCONTROL_WIDTH_16,
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.sbus = DMAC_MASTER_AHB1,
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.dbus = DMAC_MASTER_AHB1,
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.sinc = DMACCxCONTROL_INC_ENABLE,
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.dinc = DMACCxCONTROL_INC_DISABLE,
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.prot = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
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.lli_xfer_max_count = DMAC_LLI_MAX_COUNT,
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};
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/*** clocks ***/
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// TODO: In mks5lboot --mkraw put a command to specify the address of the binary,
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// for example --address 0x6000, it must be greater than 0x310 which would be the default address,
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// pass this address (0x310..128Kb) in the dfu_options flag
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// TODO: to lcd-target.c
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static void lcd_target_enable_clocks(bool enable)
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{
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clockgate_enable(CLOCKGATE_LCD, enable);
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#ifdef IPOD_NANO4G
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clockgate_enable(CLOCKGATE_LCD_2, enable);
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#endif
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}
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/*** LCD controller - low level functions ***/
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static void s5l_lcd_write_config(uint32_t config) ICODE_ATTR;
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static void s5l_lcd_write_config(uint32_t config)
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{
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while (!(LCD_STATUS & 0x2));
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udelay(1);
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LCD_CON = config;
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}
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static void s5l_lcd_write_cmd(uint16_t cmd) ICODE_ATTR;
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static void s5l_lcd_write_cmd(uint16_t cmd)
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{
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while (LCD_STATUS & 0x10);
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LCD_WCMD = cmd;
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}
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static void s5l_lcd_write_data(uint16_t data) ICODE_ATTR;
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static void s5l_lcd_write_data(uint16_t data)
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{
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while (LCD_STATUS & 0x10);
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LCD_WDATA = data;
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}
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static void s5l_lcd_send_cmd8(uint8_t cmd, int len, uint8_t *data) ICODE_ATTR;
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static void s5l_lcd_send_cmd8(uint8_t cmd, int len, uint8_t *data)
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{
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s5l_lcd_write_cmd(cmd);
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while (len--)
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s5l_lcd_write_data(*data++);
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}
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#ifdef S5L_LCD_WITH_READID
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static void s5l_lcd_recv_cmd8(uint8_t cmd, int len, uint8_t *buf)
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{
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s5l_lcd_write_cmd(cmd);
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while (len--) {
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while (!(LCD_STATUS & 0x2));
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LCD_RDATA = 0;
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while (!(LCD_STATUS & 1));
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*buf++ = LCD_DBUFF >> 1;
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}
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}
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#endif
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#define s5l_lcd_set_command_mode() s5l_lcd_write_config(lcd_cmd_mode)
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#define s5l_lcd_set_frame_mode() s5l_lcd_write_config(lcd_frame_mode)
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static void s5l_lcd_run_seq8(void *seq8)
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{
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uint8_t *seq = seq8;
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while (1) switch (*seq++)
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{
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case CMD:
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{
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uint8_t cmd = *seq++;
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int len = *seq++;
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s5l_lcd_send_cmd8(cmd, len, seq);
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seq += len;
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break;
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}
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case SLEEP:
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sleep(*seq++);
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break;
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case END:
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default:
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/* bye */
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return;
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}
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}
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#ifdef S5L_LCD_WITH_CMDSET16
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static void s5l_lcd_write_reg(uint16_t cmd, uint16_t data) ICODE_ATTR;
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static void s5l_lcd_write_reg(uint16_t cmd, uint16_t data)
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{
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s5l_lcd_write_cmd(cmd);
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s5l_lcd_write_data(data);
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}
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static void s5l_lcd_run_seq16(void *seq16)
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{
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uint16_t *seq = seq16;
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int action, param;
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uint16_t reg;
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while (1)
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{
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action = *seq & 0xff;
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param = *seq++ >> 8;
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switch (action)
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{
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case CMD:
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s5l_lcd_write_cmd(*seq++);
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break;
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case MREG:
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reg = *seq++;
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while (param--)
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s5l_lcd_write_reg(reg++, *seq++);
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break;
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case SLEEP:
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sleep(param);
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break;
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case DELAY:
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udelay(param<<6);
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break;
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case END:
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default:
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/* bye */
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return;
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}
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}
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}
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#endif /* S5L_LCD_WITH_CMDSET16 */
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/*** Update functions ***/
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/* Update the display.
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This must be called after all other LCD functions that change the display. */
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void lcd_update(void) ICODE_ATTR;
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void lcd_update(void)
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{
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lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
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}
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static void displaylcd_setup(int x, int y, int width, int height) ICODE_ATTR;
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static void displaylcd_setup(int x, int y, int width, int height)
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{
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int xe = (x + width) - 1; /* max horiz */
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int ye = (y + height) - 1; /* max vert */
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s5l_lcd_set_command_mode();
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#ifdef S5L_LCD_WITH_CMDSET16
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if (lcd_info->cmdset == LCD_CMDSET_16BIT)
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{
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s5l_lcd_write_reg(R_HORIZ_ADDR_START_POS, x);
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s5l_lcd_write_reg(R_HORIZ_ADDR_END_POS, xe);
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s5l_lcd_write_reg(R_VERT_ADDR_START_POS, y);
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s5l_lcd_write_reg(R_VERT_ADDR_END_POS, ye);
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s5l_lcd_write_reg(R_HORIZ_GRAM_ADDR_SET, x);
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s5l_lcd_write_reg(R_VERT_GRAM_ADDR_SET, y);
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s5l_lcd_write_cmd(R_WRITE_DATA_TO_GRAM);
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}
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else
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#endif
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{
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uint8_t col[] = { x >> 8, x & 0xff, xe >> 8, xe & 0xff };
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uint8_t row[] = { y >> 8, y & 0xff, ye >> 8, ye & 0xff };
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s5l_lcd_send_cmd8(R_COLUMN_ADDR_SET, 4, col);
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s5l_lcd_send_cmd8(R_ROW_ADDR_SET, 4, row);
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s5l_lcd_write_cmd(R_MEMORY_WRITE);
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}
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}
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static void displaylcd_dma(int pixels) ICODE_ATTR;
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static void displaylcd_dma(int pixels)
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{
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s5l_lcd_set_frame_mode();
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commit_dcache();
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dmac_ch_queue(&lcd_dma_ch, lcd_dblbuf,
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(void*)S5L8702_DADDR_PERI_LCD_WR, pixels*2, NULL);
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}
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// TODO: wait if there is a DMA transfer in progress
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static void displaylcd_wait_dma(void) ICODE_ATTR;
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static void displaylcd_wait_dma(void)
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{
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while (dmac_ch_running(&lcd_dma_ch))
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yield();
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}
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/* Update a fraction of the display. */
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void lcd_update_rect(int, int, int, int) ICODE_ATTR;
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void lcd_update_rect(int x, int y, int width, int height)
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{
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int pixels = width * height;
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fb_data* p = FBADDR(x,y);
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uint16_t* out = lcd_dblbuf[0];
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/* FIXME: ISR()->panicf()->lcd_update() blocks forever */
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mutex_lock(&lcd_mutex);
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if (lcd_ispowered)
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{
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// XXX: We contemplate the case where the LCD has entered SLEEP,
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// the s5l_lcd_set_command_mode() writes LCD_CONFIG
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// XXX: It is also possible that if the LCD clockgate has been disabled,
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// the LCD_CONFIG = xxx may still be blocked by the while(status == ok),
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// since it does not check the same status bit as when writing command/data
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displaylcd_wait_dma();
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displaylcd_setup(x, y, width, height);
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/* Copy display bitmap to hardware */
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if (LCD_WIDTH == width) {
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/* Write all lines at once */
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memcpy(out, p, pixels * 2);
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} else {
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do {
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/* Write a single line */
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memcpy(out, p, width * 2);
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p += LCD_WIDTH;
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out += width;
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} while (--height);
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}
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displaylcd_dma(pixels);
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}
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mutex_unlock(&lcd_mutex);
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}
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/* Line write helper function for lcd_yuv_blit. Writes two lines of yuv420. */
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extern void lcd_write_yuv420_lines(unsigned char const * const src[3],
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uint16_t* outbuf,
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int width,
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int stride);
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/* Blit a YUV bitmap directly to the LCD */
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void lcd_blit_yuv(unsigned char * const src[3],
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int src_x, int src_y, int stride,
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int x, int y, int width, int height) ICODE_ATTR;
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void lcd_blit_yuv(unsigned char * const src[3],
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int src_x, int src_y, int stride,
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int x, int y, int width, int height)
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{
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unsigned int z;
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unsigned char const * yuv_src[3];
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width = (width + 1) & ~1; /* ensure width is even */
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int pixels = width * height;
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uint16_t* out = lcd_dblbuf[0];
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z = stride * src_y;
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yuv_src[0] = src[0] + z + src_x;
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yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1);
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yuv_src[2] = src[2] + (yuv_src[1] - src[1]);
|
|
|
|
/* TODO: ISR()->panicf()->lcd_update() blocks forever */
|
|
mutex_lock(&lcd_mutex);
|
|
if (lcd_ispowered)
|
|
{
|
|
displaylcd_wait_dma();
|
|
|
|
displaylcd_setup(x, y, width, height);
|
|
|
|
height >>= 1;
|
|
|
|
do {
|
|
lcd_write_yuv420_lines(yuv_src, out, width, stride);
|
|
yuv_src[0] += stride << 1;
|
|
yuv_src[1] += stride >> 1; /* Skip down one chroma line */
|
|
yuv_src[2] += stride >> 1;
|
|
out += width << 1;
|
|
} while (--height);
|
|
|
|
displaylcd_dma(pixels);
|
|
}
|
|
mutex_unlock(&lcd_mutex);
|
|
}
|
|
|
|
|
|
/*** hardware configuration ***/
|
|
|
|
int lcd_default_contrast(void)
|
|
{
|
|
return 0x1f;
|
|
}
|
|
|
|
void lcd_set_contrast(int val)
|
|
{
|
|
(void)val;
|
|
}
|
|
|
|
void lcd_set_invert_display(bool yesno)
|
|
{
|
|
(void)yesno;
|
|
}
|
|
|
|
void lcd_set_flip(bool yesno)
|
|
{
|
|
(void)yesno;
|
|
}
|
|
|
|
#if defined(HAVE_LCD_ENABLE) || defined(HAVE_LCD_SLEEP)
|
|
bool lcd_active(void)
|
|
{
|
|
return lcd_ispowered;
|
|
}
|
|
#endif
|
|
|
|
#if defined(HAVE_LCD_SHUTDOWN) || defined(HAVE_LCD_SLEEP)
|
|
static void lcd_powersave(void)
|
|
{
|
|
mutex_lock(&lcd_mutex);
|
|
|
|
displaylcd_wait_dma();
|
|
// XXX: Do not change modes while data is being sent
|
|
s5l_lcd_set_command_mode();
|
|
lcd_run_seq(lcd_info->seq_sleep);
|
|
|
|
lcd_target_enable_clocks(false);
|
|
|
|
lcd_ispowered = false;
|
|
|
|
mutex_unlock(&lcd_mutex);
|
|
}
|
|
#endif /* HAVE_LCD_SHUTDOWN || HAVE_LCD_SLEEP */
|
|
|
|
#ifdef HAVE_LCD_SHUTDOWN
|
|
void lcd_shutdown(void)
|
|
{
|
|
backlight_hw_kill(); /* Kill the backlight, instantly. */
|
|
lcd_powersave();
|
|
}
|
|
#endif
|
|
|
|
#ifdef HAVE_LCD_SLEEP
|
|
void lcd_sleep(void)
|
|
{
|
|
lcd_powersave();
|
|
}
|
|
|
|
void lcd_awake(void)
|
|
{
|
|
mutex_lock(&lcd_mutex);
|
|
|
|
lcd_target_enable_clocks(true);
|
|
// XXX: Do not change modes while data is being sent
|
|
s5l_lcd_set_command_mode();
|
|
lcd_run_seq(lcd_info->seq_awake);
|
|
lcd_ispowered = true; // XXX: we have to put the lcd_ispowered before the lcd_update()
|
|
|
|
lcd_update(); // XXX: update the display and wait for the update to finish before returning,
|
|
|
|
displaylcd_wait_dma(); // we should really do sleep_out + lcd_update + display_on,
|
|
// we can put a command in the sequence to do it
|
|
|
|
mutex_unlock(&lcd_mutex);
|
|
send_event(LCD_EVENT_ACTIVATION, NULL);
|
|
}
|
|
#endif
|
|
|
|
#ifdef S5L_LCD_WITH_READID
|
|
// TODO: protect it with mutex and while(dma) if you want to call it from other places (e.g. DEBUG)
|
|
void lcd_read_display_id(int mpuiface, uint8_t *lcd_id)
|
|
{
|
|
s5l_lcd_write_config(
|
|
(mpuiface == LCD_MPUIFACE_SERIAL) ? LCD_MODE_S8 : LCD_MODE_P8);
|
|
s5l_lcd_recv_cmd8(4, 4, lcd_id);
|
|
}
|
|
#endif
|
|
|
|
/* LCD init */
|
|
void lcd_init_device(void)
|
|
{
|
|
mutex_init(&lcd_mutex);
|
|
|
|
lcd_target_enable_clocks(true);
|
|
#if defined(IPOD_6G) || defined(IPOD_NANO3G)
|
|
LCD_PHTIME = 0x33;
|
|
#elif defined(IPOD_NANO4G) && defined(BOOTLOADER)
|
|
cg16_config(&CG16_LCD, true, CG16_SEL_PLL0, 16, 1, 0x0);
|
|
s5l_lcd_write_config(LCD_MODE_S9);
|
|
cg16_config(&CG16_LCD, false, CG16_SEL_PLL0, 16, 1, 0x0);
|
|
LCD_PHTIME = 0x11;
|
|
#endif
|
|
|
|
lcd_info = lcd_target_get_info();
|
|
lcd_type = lcd_info->lcd_type;
|
|
|
|
/* select mode to send commands */
|
|
#ifdef S5L_LCD_WITH_CMDSET16
|
|
if (lcd_info->cmdset == LCD_CMDSET_16BIT)
|
|
{
|
|
lcd_cmd_mode = LCD_MODE_P18;
|
|
lcd_run_seq = s5l_lcd_run_seq16;
|
|
}
|
|
else /* LCD_CMDSET_8BIT */
|
|
#endif
|
|
{
|
|
if (lcd_info->mpuiface == LCD_MPUIFACE_SERIAL)
|
|
lcd_cmd_mode = LCD_MODE_S8;
|
|
else
|
|
lcd_cmd_mode = LCD_MODE_P8;
|
|
lcd_run_seq = s5l_lcd_run_seq8;
|
|
}
|
|
|
|
/* select mode to send RGB565 data */
|
|
if (lcd_info->mpuiface == LCD_MPUIFACE_PAR9)
|
|
lcd_frame_mode = LCD_MODE_P9;
|
|
else if (lcd_info->mpuiface == LCD_MPUIFACE_PAR18)
|
|
lcd_frame_mode = LCD_MODE_P16;
|
|
else /* LCD_MPUIFACE_SERIAL */
|
|
lcd_frame_mode = LCD_MODE_S9;
|
|
|
|
s5l_lcd_set_command_mode();
|
|
|
|
/* Configure DMA channel */ // TODO: this right after mutex_init()
|
|
dmac_ch_init(&lcd_dma_ch, &lcd_dma_ch_cfg);
|
|
|
|
#ifdef BOOTLOADER
|
|
lcd_run_seq(lcd_info->seq_init);
|
|
#endif
|
|
|
|
lcd_ispowered = true;
|
|
}
|