mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-12-07 13:45:03 -05:00
adbd0125fd
Check for the ES9018K2M dac in the bootloader for hw1/hw2 devices. Assume that all devices newer than hw2 have ES9018K2M DAC unconditionally. All devices will now report the correct hw revision in the debug menu under Device Data. Add devicedata.version field, current version 0. Rename device_data.lcd_version to device_data.hw_rev. hw2 devices with older bootloaders which ID as hw1 are special- cased to keep using hwvol on them. They should still upgrade though. Change-Id: If0fd5ce3bc6e85e511047721ec18e42fb89312e7
408 lines
12 KiB
C
408 lines
12 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include <string.h>
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#include "mips.h"
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#include "panic.h"
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#include "button.h"
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#include "gpio-x1000.h"
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#include "dma-x1000.h"
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#include "irq-x1000.h"
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#include "clk-x1000.h"
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#include "boot-x1000.h"
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#include "x1000/cpm.h"
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#include "x1000/ost.h"
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#include "x1000/tcu.h"
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#include "x1000/wdt.h"
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#include "x1000/intc.h"
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#include "x1000/msc.h"
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#include "x1000/aic.h"
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#if defined(HAVE_DEVICEDATA)
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#include "devicedata.h"
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#endif
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#if defined(EROS_QN)
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#include "eros_qn_codec.h"
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#endif
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#ifdef X1000_CPUIDLE_STATS
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int __cpu_idle_avg = 0;
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int __cpu_idle_cur = 0;
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uint32_t __cpu_idle_ticks = 0;
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uint32_t __cpu_idle_reftick = 0;
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#endif
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/* Prepare the CPU to process interrupts, but don't enable them yet */
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static void system_init_irq(void) INIT_ATTR;
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static void system_init_irq(void)
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{
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/* Mask all interrupts */
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jz_set(INTC_MSK(0), 0xffffffff);
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jz_set(INTC_MSK(1), 0xffffffff);
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/* It's safe to unmask these unconditionally */
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jz_clr(INTC_MSK(0), (1 << IRQ0_GPIO0) | (1 << IRQ0_GPIO1) |
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(1 << IRQ0_GPIO2) | (1 << IRQ0_GPIO3) |
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(1 << IRQ0_TCU1));
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/* Setup CP0 registers */
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write_c0_status(M_StatusCU0 | M_StatusIM2 | M_StatusIM3);
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write_c0_cause(M_CauseIV);
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}
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/* First function called by crt0.S */
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void system_early_init(void)
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{
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#if defined(FIIO_M3K) && !defined(BOOTLOADER)
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/* HACK for compatibility: CPM scratchpad has undefined contents at
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* time of reset and old bootloader revisions don't initialize it.
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* Therefore we can't rely on its contents on the FiiO M3K. This does
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* kind of break the entire point of boot flags, but right now they
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* are really only used by the bootloader so it's not a huge issue.
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* This hack should keep everything working as usual. */
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if(jz_readf(CPM_MPCR, ON) == 0) {
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init_boot_flags();
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set_boot_flag(BOOT_FLAG_CLK_INIT);
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}
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#endif
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/* Finish up clock init */
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clk_init();
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}
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#if defined (HAVE_DEVICEDATA) && defined(EROS_QN)
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void fill_devicedata(struct device_data_t *data)
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{
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# ifdef BOOTLOADER
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memset(data->payload, 0xff, data->length);
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# if EROSQN_VER == 1
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// version 2 has newer dac, 1 has old dac.
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data->hw_rev = eros_qn_discover_dac(false) ? 2 : 1;
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# else
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// versions 3 and 4 both have new dac
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data->hw_rev = EROSQN_VER;
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# endif
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data->version = DEIVCE_DATA_VERSION;
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# else
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uint8_t hw_rev = device_data.hw_rev;
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uint8_t version = device_data.version;
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memset(data->payload, 0xff, data->length);
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data->hw_rev = hw_rev;
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data->version = version;
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# endif
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}
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#endif
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/* First thing called from Rockbox main() */
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void system_init(void)
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{
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/* Gate all clocks except CPU/bus/memory/RTC */
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REG_CPM_CLKGR = ~jz_orm(CPM_CLKGR, CPU_BIT, DDR, AHB0, APB0, RTC);
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/* Ungate timers and turn them all off by default */
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jz_writef(CPM_CLKGR, TCU(0), OST(0));
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jz_clrf(OST_ENABLE, OST1, OST2);
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jz_write(OST_1MSK, 1);
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jz_write(OST_1FLG, 0);
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jz_clr(TCU_ENABLE, 0x80ff);
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jz_set(TCU_MASK, 0xff10ff);
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jz_clr(TCU_FLAG, 0xff10ff);
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jz_set(TCU_STOP, 0x180ff);
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/* Start OST2, needed for delay timer */
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jz_writef(OST_CTRL, PRESCALE2_V(BY_4));
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jz_writef(OST_CLEAR, OST2(1));
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jz_write(OST_2CNTH, 0);
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jz_write(OST_2CNTL, 0);
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jz_setf(OST_ENABLE, OST2);
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/* Ensure CPU sleep mode is IDLE and not SLEEP */
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jz_writef(CPM_LCR, LPM_V(IDLE));
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/* All other init */
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gpio_init();
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system_init_irq();
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dma_init();
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mmu_init();
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long tgt_freq)
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{
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/* Clamp target frequency to "sane" values */
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if(tgt_freq < 0) tgt_freq = 0;
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if(tgt_freq > CPU_FREQ) tgt_freq = CPU_FREQ;
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/* Find out input clock */
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uint32_t in_freq;
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switch(jz_readf(CPM_CCR, SEL_CPLL)) {
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case 1: in_freq = clk_get(X1000_CLK_SCLK_A); break;
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case 2: in_freq = clk_get(X1000_CLK_MPLL); break;
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default: return;
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}
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/* Clamp to valid range */
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if(tgt_freq < 1)
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tgt_freq = 1;
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if(tgt_freq > (long)in_freq)
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tgt_freq = in_freq;
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/* Calculate CPU clock divider */
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uint32_t cdiv = clk_calc_div(in_freq, tgt_freq);
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if(cdiv > 16) cdiv = 16;
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if(cdiv < 1) cdiv = 1;
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/* Calculate L2 cache clock. */
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uint32_t l2div = cdiv;
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if(cdiv == 1)
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l2div = 2;
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/* Change CPU/L2 frequency */
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jz_writef(CPM_CCR, CE_CPU(1), L2DIV(l2div - 1), CDIV(cdiv - 1));
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while(jz_readf(CPM_CSR, CDIV_BUSY));
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jz_writef(CPM_CCR, CE_CPU(0));
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/* Update value for Rockbox */
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cpu_frequency = in_freq / cdiv;
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}
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#endif
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void system_reboot(void)
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{
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jz_clr(TCU_STOP, 0x10000);
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jz_writef(WDT_CTRL, PRESCALE_V(BY_4), SOURCE_V(EXT));
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jz_write(WDT_COUNT, 0);
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jz_write(WDT_DATA, X1000_EXCLK_FREQ / 1000);
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jz_write(WDT_ENABLE, 1);
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while(1);
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}
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int system_memory_guard(int mode)
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{
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/* unused */
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(void)mode;
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return 0;
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}
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/* Simple delay API -- slow path functions */
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void __udelay(uint32_t us)
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{
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while(us > MAX_UDELAY_ARG) {
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__ost_delay(MAX_UDELAY_ARG * OST_TICKS_PER_US);
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us -= MAX_UDELAY_ARG;
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}
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__ost_delay(us * OST_TICKS_PER_US);
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}
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void __mdelay(uint32_t ms)
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{
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while(ms > MAX_MDELAY_ARG) {
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__ost_delay(MAX_MDELAY_ARG * 1000 * OST_TICKS_PER_US);
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ms -= MAX_MDELAY_ARG;
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}
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__ost_delay(ms * 1000 * OST_TICKS_PER_US);
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}
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uint64_t __ost_read64(void)
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{
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int irq = disable_irq_save();
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uint64_t lcnt = REG_OST_2CNTL;
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uint64_t hcnt = REG_OST_2CNTHB;
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restore_irq(irq);
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return (hcnt << 32) | lcnt;
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}
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/* IRQ handling */
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static int irq = 0;
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static unsigned ipr0 = 0, ipr1 = 0;
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static void UIRQ(void)
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{
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panicf("Unhandled interrupt occurred: %d", irq);
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}
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#define intr(name) extern __attribute__((weak, alias("UIRQ"))) void name(void)
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/* DWC2 USB interrupt */
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#define OTG INT_USB_FUNC
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/* Main interrupts */
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intr(DMIC); intr(AIC); intr(SFC); intr(SSI0); intr(OTG); intr(AES);
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intr(TCU2); intr(TCU1); intr(TCU0); intr(CIM); intr(LCD); intr(RTC);
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intr(MSC1); intr(MSC0); intr(SCC); intr(PCM0); intr(HARB2); intr(HARB0);
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intr(CPM); intr(UART2); intr(UART1); intr(UART0); intr(DDR); intr(EFUSE);
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intr(MAC); intr(I2C2); intr(I2C1); intr(I2C0); intr(JPEG);
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intr(PDMA); intr(PDMAD); intr(PDMAM);
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/* GPIO A - 32 pins */
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intr(GPIOA00); intr(GPIOA01); intr(GPIOA02); intr(GPIOA03); intr(GPIOA04);
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intr(GPIOA05); intr(GPIOA06); intr(GPIOA07); intr(GPIOA08); intr(GPIOA09);
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intr(GPIOA10); intr(GPIOA11); intr(GPIOA12); intr(GPIOA13); intr(GPIOA14);
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intr(GPIOA15); intr(GPIOA16); intr(GPIOA17); intr(GPIOA18); intr(GPIOA19);
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intr(GPIOA20); intr(GPIOA21); intr(GPIOA22); intr(GPIOA23); intr(GPIOA24);
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intr(GPIOA25); intr(GPIOA26); intr(GPIOA27); intr(GPIOA28); intr(GPIOA29);
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intr(GPIOA30); intr(GPIOA31);
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/* GPIO B - 32 pins */
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intr(GPIOB00); intr(GPIOB01); intr(GPIOB02); intr(GPIOB03); intr(GPIOB04);
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intr(GPIOB05); intr(GPIOB06); intr(GPIOB07); intr(GPIOB08); intr(GPIOB09);
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intr(GPIOB10); intr(GPIOB11); intr(GPIOB12); intr(GPIOB13); intr(GPIOB14);
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intr(GPIOB15); intr(GPIOB16); intr(GPIOB17); intr(GPIOB18); intr(GPIOB19);
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intr(GPIOB20); intr(GPIOB21); intr(GPIOB22); intr(GPIOB23); intr(GPIOB24);
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intr(GPIOB25); intr(GPIOB26); intr(GPIOB27); intr(GPIOB28); intr(GPIOB29);
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intr(GPIOB30); intr(GPIOB31);
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/* GPIO C - 26 pins */
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intr(GPIOC00); intr(GPIOC01); intr(GPIOC02); intr(GPIOC03); intr(GPIOC04);
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intr(GPIOC05); intr(GPIOC06); intr(GPIOC07); intr(GPIOC08); intr(GPIOC09);
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intr(GPIOC10); intr(GPIOC11); intr(GPIOC12); intr(GPIOC13); intr(GPIOC14);
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intr(GPIOC15); intr(GPIOC16); intr(GPIOC17); intr(GPIOC18); intr(GPIOC19);
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intr(GPIOC20); intr(GPIOC21); intr(GPIOC22); intr(GPIOC23); intr(GPIOC24);
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intr(GPIOC25);
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/* GPIO D - 6 pins */
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intr(GPIOD00); intr(GPIOD01); intr(GPIOD02); intr(GPIOD03); intr(GPIOD04);
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intr(GPIOD05);
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/* OST interrupt -- has no IRQ number since it's got special handling */
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intr(OST);
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#undef intr
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static void(*irqvector[])(void) = {
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/* ICSR0: 0 - 31 */
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DMIC, AIC, UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, SFC,
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SSI0, UIRQ, PDMA, PDMAD, UIRQ, UIRQ, UIRQ, UIRQ,
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UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, OTG, UIRQ, AES,
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UIRQ, TCU2, TCU1, TCU0, UIRQ, UIRQ, CIM, LCD,
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/* ICSR1: 32 - 63 */
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RTC, UIRQ, UIRQ, UIRQ, MSC1, MSC0, SCC, UIRQ,
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PCM0, UIRQ, UIRQ, UIRQ, HARB2, UIRQ, HARB0, CPM,
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UIRQ, UART2, UART1, UART0, DDR, UIRQ, EFUSE, MAC,
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UIRQ, UIRQ, I2C2, I2C1, I2C0, PDMAM, JPEG, UIRQ,
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/* GPIO A: 64 - 95 */
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GPIOA00, GPIOA01, GPIOA02, GPIOA03, GPIOA04, GPIOA05, GPIOA06, GPIOA07,
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GPIOA08, GPIOA09, GPIOA10, GPIOA11, GPIOA12, GPIOA13, GPIOA14, GPIOA15,
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GPIOA16, GPIOA17, GPIOA18, GPIOA19, GPIOA20, GPIOA21, GPIOA22, GPIOA23,
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GPIOA24, GPIOA25, GPIOA26, GPIOA27, GPIOA28, GPIOA29, GPIOA30, GPIOA31,
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/* GPIO B: 96 - 127 */
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GPIOB00, GPIOB01, GPIOB02, GPIOB03, GPIOB04, GPIOB05, GPIOB06, GPIOB07,
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GPIOB08, GPIOB09, GPIOB10, GPIOB11, GPIOB12, GPIOB13, GPIOB14, GPIOB15,
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GPIOB16, GPIOB17, GPIOB18, GPIOB19, GPIOB20, GPIOB21, GPIOB22, GPIOB23,
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GPIOB24, GPIOB25, GPIOB26, GPIOB27, GPIOB28, GPIOB29, GPIOB30, GPIOB31,
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/* GPIO C: 128 - 159 */
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GPIOC00, GPIOC01, GPIOC02, GPIOC03, GPIOC04, GPIOC05, GPIOC06, GPIOC07,
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GPIOC08, GPIOC09, GPIOC10, GPIOC11, GPIOC12, GPIOC13, GPIOC14, GPIOC15,
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GPIOC16, GPIOC17, GPIOC18, GPIOC19, GPIOC20, GPIOC21, GPIOC22, GPIOC23,
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GPIOC24, GPIOC25, UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, UIRQ,
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/* GPIO D: 160 - 165 */
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GPIOD00, GPIOD01, GPIOD02, GPIOD03, GPIOD04, GPIOD05,
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};
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irq_handler_t system_set_irq_handler(int irq, irq_handler_t handler)
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{
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irq_handler_t old_handler = irqvector[irq];
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irqvector[irq] = handler;
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return old_handler;
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}
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void system_enable_irq(int irq)
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{
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if(IRQ_IS_GROUP0(irq)) {
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jz_clr(INTC_MSK(0), 1 << IRQ_TO_GROUP0(irq));
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} else if(IRQ_IS_GROUP1(irq)) {
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jz_clr(INTC_MSK(1), 1 << IRQ_TO_GROUP1(irq));
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}
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}
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void system_disable_irq(int irq)
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{
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if(IRQ_IS_GROUP0(irq)) {
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jz_set(INTC_MSK(0), 1 << IRQ_TO_GROUP0(irq));
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} else if(IRQ_IS_GROUP1(irq)) {
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jz_set(INTC_MSK(1), 1 << IRQ_TO_GROUP1(irq));
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}
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}
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static int vector_gpio_irq(int port)
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{
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int n = find_first_set_bit(REG_GPIO_FLAG(port));
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if(n & 32)
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return -1;
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jz_clr(GPIO_FLAG(port), 1 << n);
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return IRQ_GPIO(port, n);
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}
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static int vector_irq(void)
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{
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int n = find_first_set_bit(ipr0);
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if(n & 32) {
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n = find_first_set_bit(ipr1);
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if(n & 32)
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return -1;
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ipr1 &= ~(1 << n);
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n += 32;
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} else {
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ipr0 &= ~(1 << n);
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}
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switch(n) {
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case IRQ0_GPIO0: n = vector_gpio_irq(GPIO_A); break;
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case IRQ0_GPIO1: n = vector_gpio_irq(GPIO_B); break;
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case IRQ0_GPIO2: n = vector_gpio_irq(GPIO_C); break;
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case IRQ0_GPIO3: n = vector_gpio_irq(GPIO_D); break;
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default: break;
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}
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return n;
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}
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void intr_handler(void)
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{
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unsigned long cause = read_c0_cause();
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/* OST interrupt is handled separately */
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if(cause & M_CauseIP3) {
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OST();
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return;
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}
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/* Gather pending interrupts */
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ipr0 |= REG_INTC_PND(0);
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ipr1 |= REG_INTC_PND(1);
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/* Process and dispatch interrupt */
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irq = vector_irq();
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if(irq < 0)
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return;
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irqvector[irq]();
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}
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void system_exception_wait(void)
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{
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#ifdef FIIO_M3K
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while(button_read_device() != (BUTTON_POWER|BUTTON_VOL_DOWN));
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#else
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while(1);
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#endif
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}
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