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When the bootloader starts only IRAM is available, the first task is to ask the PMU to verify if the iPod has previously been hibernated by OF. Due to memory limitations, the kernel cannot be used on this stage. This patch modifies I2C and PMU low level functions to not to depend on kernel (removes mutexes, and uses HW timer instead of current_tick), actual kernel functions are modified to be 'mutexed' wrappers of the new functions. Change-Id: I7cef9e95dedaf176dc0659315f3dc33166d5b116
181 lines
5 KiB
C
181 lines
5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $
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*
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* Copyright (C) 2009 by Bertrik Sikken
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "kernel.h"
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#include "i2c-s5l8702.h"
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/* Driver for the s5l8700 built-in I2C controller in master mode
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Both the i2c_read and i2c_write function take the following arguments:
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* slave, the address of the i2c slave device to read from / write to
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* address, optional sub-address in the i2c slave (unused if -1)
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* len, number of bytes to be transfered
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* data, pointer to data to be transfered
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A return value < 0 indicates an error.
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Note:
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* blocks the calling thread for the entire duraton of the i2c transfer but
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uses wakeup_wait/wakeup_signal to allow other threads to run.
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* ACK from slave is not checked, so functions never return an error
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*/
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static struct mutex i2c_mtx[2];
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static void i2c_on(int bus)
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{
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/* enable I2C clock */
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PWRCON(1) &= ~(1 << 4);
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IICCON(bus) = (1 << 7) | /* ACK_GEN */
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(0 << 6) | /* CLKSEL = PCLK/16 */
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(1 << 5) | /* INT_EN */
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(1 << 4) | /* IRQ clear */
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(7 << 0); /* CK_REG */
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/* serial output on */
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IICSTAT(bus) = (1 << 4);
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}
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static void i2c_off(int bus)
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{
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/* serial output off */
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IICSTAT(bus) = 0;
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/* disable I2C clock */
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PWRCON(1) |= (1 << 4);
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}
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void i2c_init()
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{
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mutex_init(&i2c_mtx[0]);
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mutex_init(&i2c_mtx[1]);
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}
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int i2c_wr(int bus, unsigned char slave, int address, int len, const unsigned char *data)
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{
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i2c_on(bus);
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long timeout = USEC_TIMER + 20000;
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/* START */
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IICDS(bus) = slave & ~1;
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IICSTAT(bus) = 0xF0;
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IICCON(bus) = 0xB3;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 1;
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if (address >= 0) {
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/* write address */
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IICDS(bus) = address;
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IICCON(bus) = 0xB3;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 2;
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}
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/* write data */
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while (len--) {
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IICDS(bus) = *data++;
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IICCON(bus) = 0xB3;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 4;
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}
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/* STOP */
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IICSTAT(bus) = 0xD0;
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IICCON(bus) = 0xB3;
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while ((IICSTAT(bus) & (1 << 5)) != 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 5;
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i2c_off(bus);
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return 0;
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}
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int i2c_rd(int bus, unsigned char slave, int address, int len, unsigned char *data)
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{
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i2c_on(bus);
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long timeout = USEC_TIMER + 20000;
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if (address >= 0) {
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/* START */
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IICDS(bus) = slave & ~1;
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IICSTAT(bus) = 0xF0;
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IICCON(bus) = 0xB3;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 1;
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/* write address */
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IICDS(bus) = address;
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IICCON(bus) = 0xB3;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 2;
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}
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/* (repeated) START */
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IICDS(bus) = slave | 1;
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IICSTAT(bus) = 0xB0;
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IICCON(bus) = 0xB3;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 3;
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while (len--) {
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IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 4;
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*data++ = IICDS(bus);
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}
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/* STOP */
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IICSTAT(bus) = 0x90;
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IICCON(bus) = 0xB3;
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while ((IICSTAT(bus) & (1 << 5)) != 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 5;
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i2c_off(bus);
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return 0;
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}
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int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
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{
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int ret;
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mutex_lock(&i2c_mtx[bus]);
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ret = i2c_wr(bus, slave, address, len, data);
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mutex_unlock(&i2c_mtx[bus]);
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return ret;
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}
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int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data)
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{
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int ret;
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mutex_lock(&i2c_mtx[bus]);
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ret = i2c_rd(bus, slave, address, len, data);
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mutex_unlock(&i2c_mtx[bus]);
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return ret;
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}
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