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f040c4c9ec
This is a preparation to introduce support for the following SoC models: S5L8720 (iPod Nano 4G, iPod Touch 2G), S5L8730 (iPod Nano 5G), S5L8723 (iPod Nano 6G) and S5L8740 (iPod Nano 7G) The whole family consists of SoCs which are similar, running ARMv6 and Thumb2 instructions, but some peripherals are located at a different address. No functional change is to be expected so far. Change-Id: If1f7669c49cf110ccc52c5234cc42ffd6f2b4e80
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
#ifndef _CONFIG_TREMOR_H
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#define _CONFIG_TREMOR_H
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#include "codeclib.h"
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#ifdef CPU_ARM
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#define _ARM_ASSEM_
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#endif
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#ifndef BYTE_ORDER
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#ifdef ROCKBOX_BIG_ENDIAN
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#define BIG_ENDIAN 1
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#define LITTLE_ENDIAN 0
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#define BYTE_ORDER BIG_ENDIAN
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#else
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#define BYTE_ORDER LITTLE_ENDIAN
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#define LITTLE_ENDIAN 1
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#define BIG_ENDIAN 0
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#endif
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#endif
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#ifndef ICODE_ATTR_TREMOR_NOT_MDCT
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#define ICODE_ATTR_TREMOR_NOT_MDCT ICODE_ATTR
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#endif
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/* Enable special handling of buffers in faster ram, not usefull when no
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such different ram is available. There are 3 different memory configurations
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* No special iram, uses double buffers to avoid copying data
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* Small special iram, copies buffers to run hottest processing in iram
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* Large iram, uses double buffers in iram */
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#ifdef USE_IRAM
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#define TREMOR_USE_IRAM
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/* Define CPU of large IRAM (PP5022/5024, S5L87XX, MCF5250) */
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#if (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) || defined(CPU_S5L87XX) || (CONFIG_CPU == MCF5250)
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/* PCM_BUFFER : 32768 byte (4096*2*4 or 2048*4*4) *
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* WINDOW_LOOKUP : 9216 Byte (256*4 + 2048*4) *
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* TOTAL : 41984 */
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#define IRAM_IBSS_SIZE 41984
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/* Define CPU of Normal IRAM (96KB) */
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#else
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/* floor and double residue buffer : 24576 Byte (2048/2*4*2*3) *
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* WINDOW_LOOKUP : 4608 Byte (128*4 + 1024*4) *
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* TOTAL : 29184 */
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#define IRAM_IBSS_SIZE 29184
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#endif
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#endif
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/* max 2 channels */
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#define CHANNELS 2
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// #define _LOW_ACCURACY_
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#endif /* _CONFIG_TREMOR_H */
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