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2669548bcd
This also includes a small SPI driver rework for ipod6g. Only the NOR flash currently uses SPI. Tested on target using View SysCfg in Debug menu. This is a part of the large iPod Nano 4G and iPod Touch 2G support patch. Credit: Cástor Muñoz <cmvidal@gmail.com> Change-Id: If2b91c1088034dd606abc6dd0b6ad73dea0152a4
158 lines
4.2 KiB
C
158 lines
4.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id:
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*
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* Copyright © 2009 Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include "config.h"
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#include "s5l87xx.h"
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#include "clocking-s5l8702.h"
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#include "spi-s5l8702.h"
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#define SPI_N_PORT 3
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static int clkdiv[SPI_N_PORT] = {4, 4, 4};
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/* configure SPI clock, speed is PClk/(div+1) (TBC) */
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void spi_clkdiv(int port, int div)
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{
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clkdiv[port] = div;
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}
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/* state: 1 -> route GPIO ports to SPI controller
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* 0 -> set GPIO to lowest power consumption
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*/
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void spi_init(int port, bool state)
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{
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uint32_t val = state ? 0x2222 : 0xEEEF;
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switch (port)
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{
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case 0:
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PCON0 = (PCON0 & ~0xffff) | val;
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break;
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#if CONFIG_CPU == S5L8702
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case 1:
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PCON6 = (PCON6 & ~0xffff0000) | (val << 16);
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break;
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case 2:
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PCON14 = (PCON14 & ~0xff000000) | (val << 24);
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PCON15 = (PCON15 & ~0xff) | (val >> 8);
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break;
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#elif CONFIG_CPU == S5L8720
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case 1:
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PCON4 = (PCON4 & ~0xff000000) | (val << 24);
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PCON5 = (PCON5 & ~0xff) | (val >> 8);
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break;
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case 2:
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/* unknown */
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break;
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#endif
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}
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}
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/* nSS pin: output LOW -> external device SLAVE
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* output HIGH -> deactivate external SLAVE device
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* input LOW -> SLAVE condition (external MASTER device)
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*/
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void spi_ce(int port, bool state)
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{
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uint32_t level = state ? 0 : 1;
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switch (port)
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{
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case 0: GPIOCMD = 0x0000e | level; break;
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#if CONFIG_CPU == S5L8702
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case 1: GPIOCMD = 0x6040e | level; break;
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case 2: GPIOCMD = 0xe060e | level; break;
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#elif CONFIG_CPU == S5L8720
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case 1: GPIOCMD = 0x4060e | level; break;
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case 2: /* unknown */ break;
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#endif
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}
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}
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void spi_prepare(int port)
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{
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clockgate_enable(SPICLKGATE(port), true);
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#if CONFIG_CPU == S5L8720
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clockgate_enable(SPICLKGATE_2(port), true);
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#endif
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SPISTATUS(port) = 0xf;
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SPICTRL(port) |= 0xc;
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SPICLKDIV(port) = clkdiv[port];
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SPIPIN(port) = 6;
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#if CONFIG_CPU == S5L8702
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SPISETUP(port) = 0x10618;
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#elif CONFIG_CPU == S5L8720
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SPIUNK40(port) = 0xffffffff;
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SPIUNK3C(port) = 0xffffffff;
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SPISETUP(port) = 0x40618;
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#endif
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SPICTRL(port) |= 0xc;
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SPICTRL(port) = 1;
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}
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void spi_release(int port)
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{
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clockgate_enable(SPICLKGATE(port), false);
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#if CONFIG_CPU == S5L8720
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clockgate_enable(SPICLKGATE_2(port), false);
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#endif
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}
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static inline void spi_wait_ready(int port)
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{
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#if CONFIG_CPU == S5L8702
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while (!(SPISTATUS(port) & 0x3e00));
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#elif CONFIG_CPU == S5L8720
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while (!(SPISTATUS(port) & 0xf800));
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#endif
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}
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uint32_t spi_write(int port, uint32_t data)
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{
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#if CONFIG_CPU == S5L8702
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SPIRXLIMIT(port) = 1;
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while ((SPISTATUS(port) & 0x1f0) == 0x100);
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#elif CONFIG_CPU == S5L8720
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SPIUNK4C(port) = 1;
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SPIRXLIMIT(port) = 1;
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// TODO: Wouldn't this be 0x7c0? so that the rule of <<2 is fulfilled in this register?
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while ((SPISTATUS(port) & 0x7f0) == 0x400);
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#endif
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SPITXDATA(port) = data;
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spi_wait_ready(port);
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return SPIRXDATA(port);
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}
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void spi_read(int port, uint32_t size, void* buf)
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{
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uint8_t* buffer = (uint8_t*)buf;
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#if CONFIG_CPU == S5L8720
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SPIUNK4C(port) = size;
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#endif
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SPIRXLIMIT(port) = size;
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SPISETUP(port) |= 1;
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while (size--)
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{
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spi_wait_ready(port);
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*buffer++ = SPIRXDATA(port);
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}
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SPISETUP(port) &= ~1;
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}
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