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68c51456ff
Tested on ipod6g (normal and bootloader builds) This is a part of the large iPod Nano 3G and iPod Nano 4G support patch. Credit: Cástor Muñoz <cmvidal@gmail.com> Change-Id: I7c21ce2ecb6f94c0b8af4b7b16b3b77c39c6a0a4
259 lines
6.8 KiB
C
259 lines
6.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $
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*
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* Copyright (C) 2009 by Bertrik Sikken
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "kernel.h"
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#include "i2c-s5l8702.h"
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#include "clocking-s5l8702.h"
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/* Driver for the s5l8702 built-in I2C controller in master mode
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Both the i2c_read and i2c_write function take the following arguments:
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* slave, the address of the i2c slave device to read from / write to
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* address, optional sub-address in the i2c slave (unused if -1)
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* len, number of bytes to be transfered
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* data, pointer to data to be transfered
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A return value > 0 indicates an error.
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Note:
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* blocks the calling thread for the entire duraton of the i2c transfer.
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*/
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static struct mutex i2c_mtx[2];
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void i2c_init()
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{
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mutex_init(&i2c_mtx[0]);
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mutex_init(&i2c_mtx[1]);
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}
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static void wait_rdy(int bus)
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{
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while (IICUNK10(bus));
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}
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static void i2c_on(int bus)
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{
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/* enable I2C clock */
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clockgate_enable(I2CCLKGATE(bus), true);
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#if CONFIG_CPU == S5L8720
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/* this clockgate is needed when ECLK is used as source clock */
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clockgate_enable(I2CCLKGATE_2(bus), true);
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udelay(5);
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#endif
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}
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static void i2c_off(int bus)
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{
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/* serial output off */
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wait_rdy(bus);
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IICSTAT(bus) = 0;
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/* disable I2C clock */
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wait_rdy(bus);
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clockgate_enable(I2CCLKGATE(bus), false);
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#if CONFIG_CPU == S5L8720
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clockgate_enable(I2CCLKGATE_2(bus), false);
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#endif
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}
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/* wait for bus not busy, or tx/rx byte (should return once
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8 data + 1 ack clocks are generated), or STOP. */
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static void i2c_wait_io(int bus)
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{
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while (((IICSTAT(bus) & (1 << 5)) != 0) &&
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((IICSTA2(bus) & ((1 << 8)|(1 << 13))) == 0)) {
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wait_rdy(bus);
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}
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IICSTA2(bus) |= (1 << 8)|(1 << 13);
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}
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static int i2c_start(int bus, unsigned char slave, bool rd)
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{
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/* configure port */
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wait_rdy(bus);
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IICCON(bus) = (0 << 8) | /* INT_EN = disabled */
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(1 << 7) | /* ACK_GEN */
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(0 << 6) | /* CLKSEL = SRCCLK/32 (TBC) */
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#if CONFIG_CPU == S5L8702
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(0 << 0); /* CK_REG */
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#elif CONFIG_CPU == S5L8720
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(1 << 0); /* CK_REG */
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#endif
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/* START */
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int mode = rd ? 0x80 : 0xC0;
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wait_rdy(bus);
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IICSTAT(bus) = mode;
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wait_rdy(bus);
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IICDS(bus) = slave | rd;
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wait_rdy(bus);
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IICSTAT(bus) = mode | 0x30;
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#if CONFIG_CPU == S5L8702
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// XXX this seems needed when ECLK is used
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wait_rdy(bus); // XXX: To solve the nano3g problem with ECLK,
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// or you can put it in either of the two i2c_wait_io(),
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// both work if you put this
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// TODO: Try on classic, maybe it's not necessary
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#endif
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i2c_wait_io(bus);
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/* check ACK */
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if (IICSTAT(bus) & 1)
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return 1;
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return 0;
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}
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static void i2c_stop(int bus)
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{
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/* STOP */
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wait_rdy(bus);
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IICSTAT(bus) &= ~0x20;
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wait_rdy(bus);
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IICCON(bus) = 0x10;
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i2c_wait_io(bus);
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}
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static int i2c_wr_internal(int bus, unsigned char slave,
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int address, int len, const unsigned char *data)
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{
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int rc = 0;
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if (i2c_start(bus, slave, false) == 0)
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{
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/* write address + data */
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const unsigned char *ptr = data;
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const unsigned char addr = address;
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if (address >= 0) {
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ptr = &addr;
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len++;
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}
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while (len--) {
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wait_rdy(bus);
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IICDS(bus) = *ptr;
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udelay(5);
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wait_rdy(bus);
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IICCON(bus) = IICCON(bus);
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i2c_wait_io(bus);
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/* check ACK */
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if (IICSTAT(bus) & 1) {
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rc = 2;
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break;
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}
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if (ptr == &addr) ptr = data;
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else ptr++;
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}
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}
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else
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rc = 1;
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i2c_stop(bus);
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return rc;
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}
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static int i2c_rd_internal(int bus, unsigned char slave, int len, unsigned char *data)
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{
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int rc = 0;
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if (i2c_start(bus, slave, true) == 0)
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{
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while (len--) {
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wait_rdy(bus);
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IICCON(bus) &= ~(len ? 0 : 0x80); /* ACK or NAK */
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i2c_wait_io(bus);
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*data++ = IICDS(bus);
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}
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}
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else
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rc = 3;
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i2c_stop(bus);
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return rc;
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}
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int i2c_wr(int bus, unsigned char slave, int address, int len, const unsigned char *data)
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{
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i2c_on(bus);
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int rc = i2c_wr_internal(bus, slave, address, len, data);
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i2c_off(bus);
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return rc;
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}
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int i2c_rd(int bus, unsigned char slave, int address, int len, unsigned char *data)
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{
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i2c_on(bus);
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int rc = i2c_wr_internal(bus, slave, address, 0, NULL);
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if (rc == 0)
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rc = i2c_rd_internal(bus, slave, len, data);
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i2c_off(bus);
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return rc;
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}
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int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
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{
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int ret;
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mutex_lock(&i2c_mtx[bus]);
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ret = i2c_wr(bus, slave, address, len, data);
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mutex_unlock(&i2c_mtx[bus]);
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return ret;
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}
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int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data)
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{
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int ret;
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mutex_lock(&i2c_mtx[bus]);
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ret = i2c_rd(bus, slave, address, len, data);
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mutex_unlock(&i2c_mtx[bus]);
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return ret;
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}
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void i2c_preinit(int bus)
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{
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#if CONFIG_CPU == S5L8702
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if (bus == 0)
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PCON3 = (PCON3 & ~0x00000ff0) | 0x00000220;
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#if 0 /* TBC */
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else if (bus == 1)
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PCON6 = (PCON6 & ~0x0ff00000) | 0x02200000;
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#endif
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#elif CONFIG_CPU == S5L8720
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if (bus == 0) {
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PCON2 = (PCON2 & ~0xf0000000) | 0x20000000;
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PCON3 = (PCON3 & ~0x0000000f) | 0x00000002;
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}
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#endif
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i2c_on(bus);
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wait_rdy(bus);
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IICADD(bus) = 0x40; /* own slave address */
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wait_rdy(bus);
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IICUNK14(bus) = 1; /* SRCCLK = ECLK */
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wait_rdy(bus);
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IICUNK18(bus) = 0;
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wait_rdy(bus);
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IICSTAT(bus) = 0x80; /* master Rx mode, serial output off */
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wait_rdy(bus);
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IICCON(bus) = 0;
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wait_rdy(bus);
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IICSTA2(bus) = 0x3f00;
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i2c_off(bus);
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}
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