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https://github.com/Rockbox/rockbox.git
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0fef17206e
Also adds support for S5L8720 initialization. This currently changes only the bootloader code for ipod6g. Tested on target. This is a part of the large iPod Nano 3G and iPod Nano 4G support patch. Credit: Cástor Muñoz <cmvidal@gmail.com> Change-Id: Ib4b5f12b701058940c1c5bd686d8ac346ae14e12
244 lines
7.1 KiB
ArmAsm
244 lines
7.1 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
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*
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* Copyright (C) 2008 by Marcoen Hirschberg
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* Copyright (C) 2008 by Denes Balatoni
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#define ASM
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#include "config.h"
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#include "cpu.h"
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.section .intvect,"ax",%progbits
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.global start
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.global _newstart
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/* Exception vectors */
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start:
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b _newstart
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ldr pc, =undef_instr_handler
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ldr pc, =software_int_handler
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ldr pc, =prefetch_abort_handler
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ldr pc, =data_abort_handler
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ldr pc, =reserved_handler
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ldr pc, =irq_handler
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ldr pc, =fiq_handler
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.ltorg
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_newstart:
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#ifndef BOOTLOADER
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/* we do not want to execute from 0x0 as iram will be mapped there */
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ldr pc, =newstart2
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.section .init.text,"ax",%progbits
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newstart2:
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#endif
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#ifdef BOOTLOADER
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/* Actually we are reallocating from load address IRAM0:0000 or
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* IRAM1:0000 to exec address IRAM1:0800.
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* Note that vector section is also reallocated to IRAM0:0000.
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*/
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/* Reallocate from IRAM0:0000 or IRAM1:0000 to IRAM1:0800 */
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/* _movestart and _moveend must be already aligned to 32-byte */
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_rtpc:
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sub r11, pc, #8 /* subtract 8 for pipeline */
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sub r11, #_rtpc-start /* _src_start = runtime start: address */
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/* [start .. start+_movelen] -> [_movestart .. _moveend] */
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ldr r1, =_moveend
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ldr r2, =_movestart
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sub r3, r1, r2 /* _movelen = _moveend - _movestart */
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add r0, r11, r3 /* _src_end = _src_start + _movelen */
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1:
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ldmdb r0!, {r3-r10}
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stmdb r1!, {r3-r10}
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cmp r2, r1
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blt 1b
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/* copy vector section to start of IRAM0 (it will be mapped to 0x0) */
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/* [start .. _newstart] -> [IRAM0_START .. IRAM0_START+vect_len] */
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mov r0, r11 // src start
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ldr r1, =IRAM0_ORIG // dst start
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add r2, r1, #_newstart-start // dst end
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2:
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ldmia r0!, {r3-r10}
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stmia r1!, {r3-r10}
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cmp r1, r2
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blt 2b
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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.section .init.text,"ax",%progbits
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.global start_loc
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start_loc:
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#endif /* BOOTLOADER */
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#if defined(IPOD_6G) || defined(IPOD_NANO3G)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x1000
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bic r0, r0, #0x5
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mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
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.cleancache:
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mrc p15, 0, r15, c7, c10, 3 /* test and clean dcache */
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bne .cleancache
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
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#elif defined(IPOD_NANO4G)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x1000
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bic r0, r0, #0x5
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mcr p15, 0, r0, c1, c0, 0 /* disable caches and protection unit */
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate dcache */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
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mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffer */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate all unlocked entries in TLB */
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mcr p15, 0, r0, c13, c0, 0 /* disable context id register */
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/* XXX: arm1176jaf page 249/972 */
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// TODO: put it in mmu-armv6.S
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// mcr p15, 0, r0, c2, c0, 2 /* write translation table control register (set backwards compatiblity) */
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#endif
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/* reset VIC controller */ // TODO: this could go to system_init()
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ldr r1, =0x38e00000
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add r2, r1, #0x00001000
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add r3, r1, #0x00002000
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sub r4, r0, #1
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str r4, [r1,#0x14]
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str r4, [r2,#0x14]
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str r4, [r1,#0xf00]
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str r4, [r2,#0xf00]
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str r4, [r3,#0x08]
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str r4, [r3,#0x0c]
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str r0, [r1,#0x14] // TODO: This is not done by s5l8720, and I don't think it's necessary for s5l8702
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str r0, [r2,#0x14]
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#if defined(BOOTLOADER)
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/* SPI speed is limited when icache is not active. Not worth
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* activating dcache, it is almost useless on pre-init stage
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* and the TLB needs 16Kb in detriment of the bootloader.
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*/
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #1<<12 /* enable icache */
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mcr p15, 0, r0, c1, c0, 0
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#else
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bl memory_init
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/* Copy interrupt vectors to iram */
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ldr r2, =_intvectstart
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ldr r3, =_intvectend
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ldr r4, =_intvectcopy
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Copy icode and data to ram */
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ldr r2, =_iramstart
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ldr r3, =_iramend
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ldr r4, =_iramcopy
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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/* Initialise ibss section to zero */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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#endif
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2
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ldr sp, =_irqstackend
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1
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ldr sp, =_fiqstackend
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/* Let svc, abort and undefined modes use irq stack */
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msr cpsr_c, #0xd3
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ldr sp, =_irqstackend
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msr cpsr_c, #0xd7
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ldr sp, =_irqstackend
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msr cpsr_c, #0xdb
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ldr sp, =_irqstackend
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/* Switch to sys mode */
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msr cpsr_c, #0xdf
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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ldr r2, =stackbegin
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ldr r3, =0xdeadbeef
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1:
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cmp sp, r2
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strhi r3, [r2], #4
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bhi 1b
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b main
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#ifdef BOOTLOADER
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/* Initialise bss section to zero */
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.global bss_init
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.type bss_init, %function
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bss_init:
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stmfd sp!, {r4-r9,lr}
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ldr r0, =_edata
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ldr r1, =_end
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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mov r8, #0
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mov r9, #0
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b 2f
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.align 5 /* cache line size */
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1:
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stmia r0!, {r2-r9}
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2:
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cmp r0, r1
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blt 1b
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ldmpc regs=r4-r9
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.ltorg
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#endif
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