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d14ddcafd5
To keep the code size small, this hardcodes the D-Cache line size and set/way information (which is defined by the target and should be fixed for a given CPU) and assumes there is only one level of cache. Change-Id: Ia6d0e6a87b5dbfc6c39bda83b58461ed8767edf6
34 lines
1.3 KiB
C
34 lines
1.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef CPUCACHE_ARMV7M_H
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#define CPUCACHE_ARMV7M_H
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#include "cpucache-arm.h"
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#include "cpu.h"
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#define arm_dsb() asm volatile("dsb" ::: "memory")
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#define arm_isb() asm volatile("isb" ::: "memory")
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/* Discard entire icache and dcache, generally only used
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* when first enabling the caches. */
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void __discard_idcache(void);
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#endif /* CPUCACHE_ARMV7M_H */
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