mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-11-21 11:02:45 -05:00
adb978a44d
Fix CGU_DBOP setting Set PCLK to the exact frequency (62MHz, not the maximal frequency) Use a better comment for CLK_DIV macro Use preprocessor safety checks for clock divider sizes to avoid future mistakes (not for SD_IDENT frequency since that check is handled by mci_set_clock_divider) Use maximal IDE frequency of 66MHz (like OF), not 90MHz like written in AS3525 datasheet. The IDE chip is somehow linked to internal storage, and a too high frequency could affect the storage driver. Use the same DBOP frequency of 32MHz for all models (like OF, verified clip, fuze, e200v2 and m200v4), compromise between performance and battery life could be added in the future for each target Performance increase on Sansa Fuze with DBOP freq. set to 64MHz: +12% fps for lcd_update, +1% fps for yuv Thanks to daytona955 on the forums for his help git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20923 a1c6a512-1295-4272-9138-f99709370657
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/***************************************************************************
|
|
* __________ __ ___.
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
|
* \/ \/ \/ \/ \/
|
|
* $Id$
|
|
*
|
|
* Copyright © 2008 Rafaël Carré
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; either version 2
|
|
* of the License, or (at your option) any later version.
|
|
*
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
|
* KIND, either express or implied.
|
|
*
|
|
****************************************************************************/
|
|
#ifndef CLOCK_TARGET_H
|
|
#define CLOCK_TARGET_H
|
|
|
|
/* returns clock divider, given maximal target frequency and clock reference */
|
|
#define CLK_DIV(ref, target) ((ref + target - 1) / target)
|
|
|
|
/* PLL */
|
|
|
|
#define AS3525_PLLA_FREQ 248000000
|
|
#define AS3525_PLLA_SETTING 0x261F
|
|
|
|
/* CPU */
|
|
|
|
/* ensure that PLLA_FREQ * prediv == CPUFREQ_MAX */
|
|
#define AS3525_CPU_PREDIV 0 /* div = 1/1 */
|
|
|
|
#define CPUFREQ_MAX 248000000
|
|
|
|
#define CPUFREQ_DEFAULT 24800000
|
|
|
|
#define CPUFREQ_NORMAL 31000000
|
|
|
|
/* peripherals */
|
|
|
|
#define AS3525_PCLK_FREQ 62000000
|
|
#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
|
|
#error PCLK frequency is too low : clock divider will not fit !
|
|
#endif
|
|
|
|
#define AS3525_IDE_FREQ 66000000
|
|
#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
|
|
#error IDE frequency is too low : clock divider will not fit !
|
|
#endif
|
|
|
|
#define AS3525_I2C_FREQ 400000
|
|
#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_I2C_FREQ)) >= (1<<16) /* 2*8 bits */
|
|
#error I2C frequency is too low : clock divider will not fit !
|
|
#endif
|
|
|
|
#define AS3525_DBOP_FREQ 32000000
|
|
#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
|
|
#error DBOP frequency is too low : clock divider will not fit !
|
|
#endif
|
|
|
|
#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
|
|
|
|
#endif /* CLOCK_TARGET_H */
|