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3ed9fb3115
M-profile cores manage interrupts differently from classic cores and lack the FIQ. Split the interrupt management parts out into separate headers but keep the endian swapping routines (which are not profile-dependent) in the common system-arm header. The initial part of the vector table is common to all Cortex-M CPUs and is intended to be included by the target linker script, with the vendor-specific part of the vector table appended to it. Change-Id: Ib2ad5b9dc41db27940e39033cfef4308923db66d
349 lines
9.3 KiB
C
349 lines
9.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 Randy D. Wood
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "lcd.h"
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#ifdef HAVE_REMOTE_LCD
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#include "lcd-remote.h"
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#endif
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#include "scroll_engine.h"
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#include "thread.h"
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#include "kernel.h"
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#include "button.h"
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#include "file.h"
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#include "audio.h"
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#include "system.h"
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#include "i2c.h"
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#include "adc.h"
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#include "string.h"
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#include "core_alloc.h"
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#include "storage.h"
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#include "rolo.h"
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#include "loader_strerror.h"
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#if defined(MI4_FORMAT)
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#include "mi4-loader.h"
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#define LOAD_FIRMWARE(a,b,c) load_mi4(a,b,c)
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#elif defined(RKW_FORMAT)
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#include "rkw-loader.h"
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#define LOAD_FIRMWARE(a,b,c) load_rkw(a,b,c)
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#else
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#include "rb-loader.h"
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#define LOAD_FIRMWARE(a,b,c) load_firmware(a,b,c)
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#endif
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#if defined(HAVE_BOOTDATA) && !defined(SIMULATOR)
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#include "multiboot.h"
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#include "bootdata.h"
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#include "crc32.h"
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#endif
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#if defined(HAVE_DEVICEDATA) && !defined(SIMULATOR)
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#include "devicedata.h"
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#endif
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#if CONFIG_CPU == AS3525v2
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#include "ascodec.h"
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#endif
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#if defined(FIIO_M3K)
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#include "backlight-target.h"
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#endif
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#define IRQ0_EDGE_TRIGGER 0x80
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static int rolo_handle;
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#ifdef CPU_PP
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/* Handle the COP properly - it needs to jump to a function outside SDRAM while
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* the new firmware is being loaded, and then jump to the start of SDRAM
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* TODO: Use the mailboxes built into the PP processor for this
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*/
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#if NUM_CORES > 1
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volatile unsigned char IDATA_ATTR cpu_message = 0;
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volatile unsigned char IDATA_ATTR cpu_reply = 0;
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extern int cop_idlestackbegin[];
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void rolo_restart_cop(void) ICODE_ATTR;
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void rolo_restart_cop(void)
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{
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if (CURRENT_CORE == CPU)
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{
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/* There should be free thread slots aplenty */
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create_thread(rolo_restart_cop, cop_idlestackbegin, IDLE_STACK_SIZE,
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0, "rolo COP" IF_PRIO(, PRIORITY_REALTIME)
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IF_COP(, COP));
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return;
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}
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COP_INT_DIS = -1;
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/* Invalidate cache */
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commit_discard_idcache();
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/* Disable cache */
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CACHE_CTL = CACHE_CTL_DISABLE;
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/* Tell the main core that we're ready to reload */
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cpu_reply = 1;
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/* Wait while RoLo loads the image into SDRAM */
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/* TODO: Accept checksum failure gracefully */
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while(cpu_message != 1);
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/* Acknowledge the CPU and then reload */
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cpu_reply = 2;
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asm volatile(
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"bx %0 \n"
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: : "r"(DRAM_START)
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);
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}
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#endif /* NUM_CORES > 1 */
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#endif /* CPU_PP */
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static void rolo_error(const char *text)
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{
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rolo_handle = core_free(rolo_handle);
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lcd_clear_display();
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lcd_puts(0, 0, "ROLO error:");
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lcd_puts_scroll(0, 1, text);
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lcd_update();
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button_get(true);
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button_get(true);
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button_get(true);
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lcd_scroll_stop();
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}
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#if CONFIG_CPU == IMX31L || CONFIG_CPU == RK27XX || CONFIG_CPU == X1000
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/* this is in firmware/target/arm/imx31/rolo_restart.c for IMX31 */
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/* this is in firmware/target/arm/rk27xx/rolo_restart.c for rk27xx */
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/* this is in firmware/target/mips/ingenic_x1000/boot-x1000.c for X1000 */
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extern void rolo_restart(const unsigned char* source, unsigned char* dest,
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int length);
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#else
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/* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
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targets that are low on iram, like the gigabeat F/X */
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void rolo_restart(const unsigned char* source, unsigned char* dest,
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long length) __attribute__ ((section(".icode")));
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void rolo_restart(const unsigned char* source, unsigned char* dest,
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long length)
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{
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long i;
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unsigned char* localdest = dest;
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/* This is the equivalent of a call to memcpy() but this must be done from
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iram to avoid overwriting itself and we don't want to depend on memcpy()
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always being in iram */
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for(i = 0;i < length;i++)
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*localdest++ = *source++;
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#if defined(CPU_COLDFIRE)
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asm (
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"movec.l %0,%%vbr \n"
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"move.l (%0)+,%%sp \n"
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"move.l (%0),%0 \n"
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"jmp (%0) \n"
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: : "a"(dest)
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);
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#elif defined(CPU_PP)
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CPU_INT_DIS = -1;
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/* Flush cache */
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commit_discard_idcache();
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/* Disable cache */
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CACHE_CTL = CACHE_CTL_DISABLE;
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/* Reset the memory mapping registers to zero */
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{
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volatile unsigned long *mmap_reg;
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for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
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*mmap_reg = 0;
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}
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#if NUM_CORES > 1
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/* Tell the COP it's safe to continue rebooting */
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cpu_message = 1;
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/* Wait for the COP to tell us it is rebooting */
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while(cpu_reply != 2);
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#endif
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asm volatile(
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"bx %0 \n"
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: : "r"(DRAM_START)
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);
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#elif defined(CPU_ARM)
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/* Flush and invalidate caches */
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commit_discard_idcache();
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asm volatile(
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"bx %0 \n"
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: : "r"(dest)
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);
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#elif defined(CPU_MIPS)
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commit_discard_idcache();
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asm volatile(
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"jr %0 \n"
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"nop\n"
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: : "r"(dest)
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);
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#endif
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}
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#endif
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/* This is assigned in the linker control file */
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extern unsigned long loadaddress;
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/***************************************************************************
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*
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* Name: rolo_load(const char *filename)
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* Filename must be a fully defined filename including the path and extension
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*
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***************************************************************************/
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int rolo_load(const char* filename)
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{
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unsigned char* ramstart = (void*)&loadaddress;
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unsigned char* filebuf;
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size_t filebuf_size;
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int err, length;
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lcd_clear_display();
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lcd_puts(0, 0, "ROLO...");
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lcd_puts(0, 1, "Loading");
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lcd_update();
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#ifdef HAVE_REMOTE_LCD
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lcd_remote_clear_display();
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lcd_remote_puts(0, 0, "ROLO...");
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lcd_remote_puts(0, 1, "Loading");
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lcd_remote_update();
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#endif
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audio_hard_stop();
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/* get the system buffer. release only in case of error, otherwise
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* we don't return anyway */
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rolo_handle = core_alloc_maximum(&filebuf_size, &buflib_ops_locked);
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if (rolo_handle < 0)
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{
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rolo_error("OOM");
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return -1;
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}
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filebuf = core_get_data(rolo_handle);
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err = LOAD_FIRMWARE(filebuf, filename, filebuf_size);
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#if defined(HAVE_BOOTDATA) && !defined(SIMULATOR)
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// Write bootdata as long as the existing bootdata is valid
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if (boot_data_valid)
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{
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int volume = 0;
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if (boot_data.version == 0)
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volume = boot_data._boot_volume;
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else if (boot_data.version == 1)
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{
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for (int i = 0; i < NUM_VOLUMES; ++i)
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{
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if (volume_drive(i) == boot_data.boot_drive &&
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volume_partition(i) == boot_data.boot_partition)
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{
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volume = i;
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break;
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}
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}
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}
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write_bootdata(filebuf, filebuf_size, volume);
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}
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#endif
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#if defined(HAVE_DEVICEDATA)
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write_devicedata(filebuf, filebuf_size);
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#endif
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if (err <= 0)
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{
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rolo_error(loader_strerror(err));
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return -1;
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}
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else
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length = err;
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#if defined(CPU_PP) && NUM_CORES > 1
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lcd_puts(0, 2, "Waiting for coprocessor...");
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lcd_update();
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rolo_restart_cop();
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/* Wait for COP to be in safe code */
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while(cpu_reply != 1);
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lcd_puts(0, 2, " ");
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lcd_update();
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#endif
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#ifdef HAVE_STORAGE_FLUSH
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lcd_puts(0, 1, "Flushing storage buffers");
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lcd_update();
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storage_flush();
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#endif
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lcd_puts(0, 1, "Executing");
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lcd_update();
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#ifdef HAVE_REMOTE_LCD
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lcd_remote_puts(0, 1, "Executing");
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lcd_remote_update();
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#endif
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#if defined(FIIO_M3K)
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/* Avoids the LCD backlight ramping down & up weirdly */
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backlight_hw_off();
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#endif
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adc_close();
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#if CONFIG_CPU == AS3525v2
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/* Set CVDD1 power supply to default*/
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ascodec_write_pmu(0x17, 1, 0);
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#endif
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#if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
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/* It is necessary for proper detection AMSv2 variant 1.
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* We should restore initial state of GPIOB_PIN(5) as it used for
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* variant detection, but can be changed if we switch SD card. */
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if (amsv2_variant == 1)
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GPIOB_PIN(5) = 1 << 5;
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#endif
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#if CONFIG_CPU != IMX31L /* We're not finished yet */
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#if defined(CPU_ARM_CLASSIC)
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/* Should do these together since some ARM version should never have
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* FIQ disabled and not IRQ (imx31 errata). */
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disable_interrupt(IRQ_FIQ_STATUS);
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#else
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/* Some targets have a higher disable level than HIGEST_IRQ_LEVEL */
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set_irq_level(DISABLE_INTERRUPTS);
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#endif
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#endif /* CONFIG_CPU == IMX31L */
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rolo_restart(filebuf, ramstart, length);
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/* never reached */
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return 0;
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}
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