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Our decade+old defaults are reported to trigger a failure on one user's IHIFI770c and IHIFI960, but work on their HM-603. Backing CAS latency off from 2 to 3 appears to be sufficient. What's interesting is that on paper, CL=2 should be easily attainable due to our max RAM clock of 100MHz, well within the worst-case timings of the EM639165 SDRAM. So as an experiment, this code can go back to CL=2 when we change the CPU+RAM clock speeds. IF this still proves problematic, it will be removed. Change-Id: I4a8cfa0563c076e7f25d9599a19b454f590861cd |
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