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99dd797169
Move the definition of NOCACHE_BASE to the CPU headers instead of having them copy-and-pasted in a few places. Change-Id: Ibbab27a5a07906d46dbd4dd9065f2238bc885d6b
105 lines
3.4 KiB
C
105 lines
3.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __CPU_H
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#define __CPU_H
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#include "config.h"
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#if CONFIG_CPU == MCF5249
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#include "mcf5249.h"
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#elif CONFIG_CPU == MCF5250
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#include "mcf5250.h"
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#elif (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5022)
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#include "pp5020.h"
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#elif CONFIG_CPU == PP5002
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#include "pp5002.h"
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#elif CONFIG_CPU == PP5024
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#include "pp5024.h"
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#elif CONFIG_CPU == PP6100
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#include "pp6100.h"
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#elif CONFIG_CPU == S3C2440
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#include "s3c2440.h"
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#elif CONFIG_CPU == DM320
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#include "dm320.h"
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#elif CONFIG_CPU == IMX31L
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#include "imx31l.h"
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#elif defined(CPU_TCC780X)
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#include "tcc780x.h"
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#elif defined(CPU_S5L87XX)
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#include "s5l87xx.h"
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#elif CONFIG_CPU == JZ4732
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#include "jz4740.h"
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#elif CONFIG_CPU == JZ4760B
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#include "jz4760b.h"
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#elif CONFIG_CPU == AS3525
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#include "as3525.h"
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#elif CONFIG_CPU == AS3525v2
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#include "as3525v2.h"
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#elif CONFIG_CPU == IMX233
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#include "imx233.h"
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#elif CONFIG_CPU == RK27XX
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#include "rk27xx.h"
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#elif CONFIG_CPU == X1000
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#include "x1000.h"
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#elif CONFIG_CPU == STM32H743
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#include "stm32h743.h"
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#endif
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && (defined(CPU_ARM) || defined(CPU_MIPS))
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# define HAVE_CPU_CACHE_ALIGN
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#endif
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#if defined(HAVE_CPU_CACHE_ALIGN)
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# if !defined(CACHEALIGN_BITS)
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# error "CPU header must define CACHEALIGN_BITS"
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# elif !defined(CACHEALIGN_SIZE)
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# error "CPU header must define CACHEALIGN_SIZE"
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# elif CACHEALIGN_SIZE != (1u << CACHEALIGN_BITS)
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# error "CACHEALIGN_SIZE and CACHEALIGN_BITS are inconsistent"
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# endif
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#else
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# if defined(CACHEALIGN_BITS) && defined(CACHEALIGN_SIZE)
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# error "CACHEALIGN_BITS and CACHEALIGN_SIZE must not be defined for targets with no CPU cache"
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# endif
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#endif
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/*
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* Note: NOCACHE_BASE assumes that DRAM is linearly mapped both
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* at a lower cached address and an upper uncached address, so
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* that you can add NOCACHE_BASE to the cached DRAM address to
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* get the corresponding uncached address.
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*
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* Defining NOCACHE_BASE is only required if you need plugins to
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* be able to link data at uncached addresses. If in doubt, you
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* don't need this. It's mainly of use for dual-core PortalPlayer
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* targets which need to do this for things like mutexes/queues;
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* since PP lacks hardware cache coherency, data which is writable
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* by more than one core often needs to accessed uncached.
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*/
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#if defined(NOCACHE_BASE)
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# if !defined(HAVE_CPU_CACHE_ALIGN)
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# error "NOCACHE_BASE cannot be defined on targets with no CPU cache!"
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# elif NOCACHE_BASE == 0
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# error "NOCACHE_BASE cannot be 0!"
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# endif
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#endif
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#endif /* __CPU_H */
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