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FIFO errors shouldn't be possible with hardware flow control enabled. DMA errors shouldn't occur unless a bad memory address was passed. Don't bother checking for ITCM/DTCM in the transfer setup and instead just wait for the IDMATE error; if the RM0433 reference manual is to be believed then SDMMC1 _only_ has access to AXI bus memories, and checking for all invalid destinations would be very verbose. Change-Id: I2b22b56009933e16c5adde4d36b7a906cee57791 |
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