mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-12-08 20:55:17 -05:00
eac1ca22bd
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
849 lines
52 KiB
C
849 lines
52 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stmp3700 version: 2.4.0
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* stmp3700 authors: Amaury Pouly
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_STMP3700_SSP_H__
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#define __HEADERGEN_STMP3700_SSP_H__
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#define HW_SSP_CTRL0(_n1) HW(SSP_CTRL0(_n1))
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#define HWA_SSP_CTRL0(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x0)
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#define HWT_SSP_CTRL0(_n1) HWIO_32_RW
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#define HWN_SSP_CTRL0(_n1) SSP_CTRL0
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#define HWI_SSP_CTRL0(_n1) (_n1)
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#define HW_SSP_CTRL0_SET(_n1) HW(SSP_CTRL0_SET(_n1))
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#define HWA_SSP_CTRL0_SET(_n1) (HWA_SSP_CTRL0(_n1) + 0x4)
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#define HWT_SSP_CTRL0_SET(_n1) HWIO_32_WO
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#define HWN_SSP_CTRL0_SET(_n1) SSP_CTRL0
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#define HWI_SSP_CTRL0_SET(_n1) (_n1)
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#define HW_SSP_CTRL0_CLR(_n1) HW(SSP_CTRL0_CLR(_n1))
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#define HWA_SSP_CTRL0_CLR(_n1) (HWA_SSP_CTRL0(_n1) + 0x8)
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#define HWT_SSP_CTRL0_CLR(_n1) HWIO_32_WO
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#define HWN_SSP_CTRL0_CLR(_n1) SSP_CTRL0
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#define HWI_SSP_CTRL0_CLR(_n1) (_n1)
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#define HW_SSP_CTRL0_TOG(_n1) HW(SSP_CTRL0_TOG(_n1))
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#define HWA_SSP_CTRL0_TOG(_n1) (HWA_SSP_CTRL0(_n1) + 0xc)
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#define HWT_SSP_CTRL0_TOG(_n1) HWIO_32_WO
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#define HWN_SSP_CTRL0_TOG(_n1) SSP_CTRL0
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#define HWI_SSP_CTRL0_TOG(_n1) (_n1)
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#define BP_SSP_CTRL0_SFTRST 31
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#define BM_SSP_CTRL0_SFTRST 0x80000000
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#define BF_SSP_CTRL0_SFTRST(v) (((v) & 0x1) << 31)
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#define BFM_SSP_CTRL0_SFTRST(v) BM_SSP_CTRL0_SFTRST
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#define BF_SSP_CTRL0_SFTRST_V(e) BF_SSP_CTRL0_SFTRST(BV_SSP_CTRL0_SFTRST__##e)
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#define BFM_SSP_CTRL0_SFTRST_V(v) BM_SSP_CTRL0_SFTRST
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#define BP_SSP_CTRL0_CLKGATE 30
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#define BM_SSP_CTRL0_CLKGATE 0x40000000
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#define BF_SSP_CTRL0_CLKGATE(v) (((v) & 0x1) << 30)
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#define BFM_SSP_CTRL0_CLKGATE(v) BM_SSP_CTRL0_CLKGATE
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#define BF_SSP_CTRL0_CLKGATE_V(e) BF_SSP_CTRL0_CLKGATE(BV_SSP_CTRL0_CLKGATE__##e)
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#define BFM_SSP_CTRL0_CLKGATE_V(v) BM_SSP_CTRL0_CLKGATE
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#define BP_SSP_CTRL0_RUN 29
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#define BM_SSP_CTRL0_RUN 0x20000000
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#define BF_SSP_CTRL0_RUN(v) (((v) & 0x1) << 29)
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#define BFM_SSP_CTRL0_RUN(v) BM_SSP_CTRL0_RUN
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#define BF_SSP_CTRL0_RUN_V(e) BF_SSP_CTRL0_RUN(BV_SSP_CTRL0_RUN__##e)
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#define BFM_SSP_CTRL0_RUN_V(v) BM_SSP_CTRL0_RUN
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#define BP_SSP_CTRL0_SDIO_IRQ_CHECK 28
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#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000
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#define BF_SSP_CTRL0_SDIO_IRQ_CHECK(v) (((v) & 0x1) << 28)
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#define BFM_SSP_CTRL0_SDIO_IRQ_CHECK(v) BM_SSP_CTRL0_SDIO_IRQ_CHECK
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#define BF_SSP_CTRL0_SDIO_IRQ_CHECK_V(e) BF_SSP_CTRL0_SDIO_IRQ_CHECK(BV_SSP_CTRL0_SDIO_IRQ_CHECK__##e)
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#define BFM_SSP_CTRL0_SDIO_IRQ_CHECK_V(v) BM_SSP_CTRL0_SDIO_IRQ_CHECK
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#define BP_SSP_CTRL0_LOCK_CS 27
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#define BM_SSP_CTRL0_LOCK_CS 0x8000000
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#define BF_SSP_CTRL0_LOCK_CS(v) (((v) & 0x1) << 27)
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#define BFM_SSP_CTRL0_LOCK_CS(v) BM_SSP_CTRL0_LOCK_CS
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#define BF_SSP_CTRL0_LOCK_CS_V(e) BF_SSP_CTRL0_LOCK_CS(BV_SSP_CTRL0_LOCK_CS__##e)
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#define BFM_SSP_CTRL0_LOCK_CS_V(v) BM_SSP_CTRL0_LOCK_CS
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#define BP_SSP_CTRL0_IGNORE_CRC 26
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#define BM_SSP_CTRL0_IGNORE_CRC 0x4000000
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#define BF_SSP_CTRL0_IGNORE_CRC(v) (((v) & 0x1) << 26)
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#define BFM_SSP_CTRL0_IGNORE_CRC(v) BM_SSP_CTRL0_IGNORE_CRC
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#define BF_SSP_CTRL0_IGNORE_CRC_V(e) BF_SSP_CTRL0_IGNORE_CRC(BV_SSP_CTRL0_IGNORE_CRC__##e)
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#define BFM_SSP_CTRL0_IGNORE_CRC_V(v) BM_SSP_CTRL0_IGNORE_CRC
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#define BP_SSP_CTRL0_READ 25
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#define BM_SSP_CTRL0_READ 0x2000000
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#define BF_SSP_CTRL0_READ(v) (((v) & 0x1) << 25)
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#define BFM_SSP_CTRL0_READ(v) BM_SSP_CTRL0_READ
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#define BF_SSP_CTRL0_READ_V(e) BF_SSP_CTRL0_READ(BV_SSP_CTRL0_READ__##e)
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#define BFM_SSP_CTRL0_READ_V(v) BM_SSP_CTRL0_READ
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#define BP_SSP_CTRL0_DATA_XFER 24
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#define BM_SSP_CTRL0_DATA_XFER 0x1000000
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#define BF_SSP_CTRL0_DATA_XFER(v) (((v) & 0x1) << 24)
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#define BFM_SSP_CTRL0_DATA_XFER(v) BM_SSP_CTRL0_DATA_XFER
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#define BF_SSP_CTRL0_DATA_XFER_V(e) BF_SSP_CTRL0_DATA_XFER(BV_SSP_CTRL0_DATA_XFER__##e)
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#define BFM_SSP_CTRL0_DATA_XFER_V(v) BM_SSP_CTRL0_DATA_XFER
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#define BP_SSP_CTRL0_BUS_WIDTH 22
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#define BM_SSP_CTRL0_BUS_WIDTH 0xc00000
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#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0
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#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1
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#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2
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#define BF_SSP_CTRL0_BUS_WIDTH(v) (((v) & 0x3) << 22)
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#define BFM_SSP_CTRL0_BUS_WIDTH(v) BM_SSP_CTRL0_BUS_WIDTH
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#define BF_SSP_CTRL0_BUS_WIDTH_V(e) BF_SSP_CTRL0_BUS_WIDTH(BV_SSP_CTRL0_BUS_WIDTH__##e)
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#define BFM_SSP_CTRL0_BUS_WIDTH_V(v) BM_SSP_CTRL0_BUS_WIDTH
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#define BP_SSP_CTRL0_WAIT_FOR_IRQ 21
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#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x200000
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#define BF_SSP_CTRL0_WAIT_FOR_IRQ(v) (((v) & 0x1) << 21)
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#define BFM_SSP_CTRL0_WAIT_FOR_IRQ(v) BM_SSP_CTRL0_WAIT_FOR_IRQ
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#define BF_SSP_CTRL0_WAIT_FOR_IRQ_V(e) BF_SSP_CTRL0_WAIT_FOR_IRQ(BV_SSP_CTRL0_WAIT_FOR_IRQ__##e)
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#define BFM_SSP_CTRL0_WAIT_FOR_IRQ_V(v) BM_SSP_CTRL0_WAIT_FOR_IRQ
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#define BP_SSP_CTRL0_WAIT_FOR_CMD 20
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#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x100000
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#define BF_SSP_CTRL0_WAIT_FOR_CMD(v) (((v) & 0x1) << 20)
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#define BFM_SSP_CTRL0_WAIT_FOR_CMD(v) BM_SSP_CTRL0_WAIT_FOR_CMD
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#define BF_SSP_CTRL0_WAIT_FOR_CMD_V(e) BF_SSP_CTRL0_WAIT_FOR_CMD(BV_SSP_CTRL0_WAIT_FOR_CMD__##e)
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#define BFM_SSP_CTRL0_WAIT_FOR_CMD_V(v) BM_SSP_CTRL0_WAIT_FOR_CMD
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#define BP_SSP_CTRL0_LONG_RESP 19
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#define BM_SSP_CTRL0_LONG_RESP 0x80000
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#define BF_SSP_CTRL0_LONG_RESP(v) (((v) & 0x1) << 19)
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#define BFM_SSP_CTRL0_LONG_RESP(v) BM_SSP_CTRL0_LONG_RESP
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#define BF_SSP_CTRL0_LONG_RESP_V(e) BF_SSP_CTRL0_LONG_RESP(BV_SSP_CTRL0_LONG_RESP__##e)
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#define BFM_SSP_CTRL0_LONG_RESP_V(v) BM_SSP_CTRL0_LONG_RESP
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#define BP_SSP_CTRL0_CHECK_RESP 18
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#define BM_SSP_CTRL0_CHECK_RESP 0x40000
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#define BF_SSP_CTRL0_CHECK_RESP(v) (((v) & 0x1) << 18)
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#define BFM_SSP_CTRL0_CHECK_RESP(v) BM_SSP_CTRL0_CHECK_RESP
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#define BF_SSP_CTRL0_CHECK_RESP_V(e) BF_SSP_CTRL0_CHECK_RESP(BV_SSP_CTRL0_CHECK_RESP__##e)
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#define BFM_SSP_CTRL0_CHECK_RESP_V(v) BM_SSP_CTRL0_CHECK_RESP
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#define BP_SSP_CTRL0_GET_RESP 17
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#define BM_SSP_CTRL0_GET_RESP 0x20000
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#define BF_SSP_CTRL0_GET_RESP(v) (((v) & 0x1) << 17)
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#define BFM_SSP_CTRL0_GET_RESP(v) BM_SSP_CTRL0_GET_RESP
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#define BF_SSP_CTRL0_GET_RESP_V(e) BF_SSP_CTRL0_GET_RESP(BV_SSP_CTRL0_GET_RESP__##e)
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#define BFM_SSP_CTRL0_GET_RESP_V(v) BM_SSP_CTRL0_GET_RESP
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#define BP_SSP_CTRL0_ENABLE 16
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#define BM_SSP_CTRL0_ENABLE 0x10000
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#define BF_SSP_CTRL0_ENABLE(v) (((v) & 0x1) << 16)
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#define BFM_SSP_CTRL0_ENABLE(v) BM_SSP_CTRL0_ENABLE
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#define BF_SSP_CTRL0_ENABLE_V(e) BF_SSP_CTRL0_ENABLE(BV_SSP_CTRL0_ENABLE__##e)
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#define BFM_SSP_CTRL0_ENABLE_V(v) BM_SSP_CTRL0_ENABLE
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#define BP_SSP_CTRL0_XFER_COUNT 0
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#define BM_SSP_CTRL0_XFER_COUNT 0xffff
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#define BF_SSP_CTRL0_XFER_COUNT(v) (((v) & 0xffff) << 0)
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#define BFM_SSP_CTRL0_XFER_COUNT(v) BM_SSP_CTRL0_XFER_COUNT
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#define BF_SSP_CTRL0_XFER_COUNT_V(e) BF_SSP_CTRL0_XFER_COUNT(BV_SSP_CTRL0_XFER_COUNT__##e)
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#define BFM_SSP_CTRL0_XFER_COUNT_V(v) BM_SSP_CTRL0_XFER_COUNT
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#define HW_SSP_CMD0(_n1) HW(SSP_CMD0(_n1))
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#define HWA_SSP_CMD0(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x10)
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#define HWT_SSP_CMD0(_n1) HWIO_32_RW
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#define HWN_SSP_CMD0(_n1) SSP_CMD0
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#define HWI_SSP_CMD0(_n1) (_n1)
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#define HW_SSP_CMD0_SET(_n1) HW(SSP_CMD0_SET(_n1))
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#define HWA_SSP_CMD0_SET(_n1) (HWA_SSP_CMD0(_n1) + 0x4)
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#define HWT_SSP_CMD0_SET(_n1) HWIO_32_WO
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#define HWN_SSP_CMD0_SET(_n1) SSP_CMD0
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#define HWI_SSP_CMD0_SET(_n1) (_n1)
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#define HW_SSP_CMD0_CLR(_n1) HW(SSP_CMD0_CLR(_n1))
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#define HWA_SSP_CMD0_CLR(_n1) (HWA_SSP_CMD0(_n1) + 0x8)
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#define HWT_SSP_CMD0_CLR(_n1) HWIO_32_WO
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#define HWN_SSP_CMD0_CLR(_n1) SSP_CMD0
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#define HWI_SSP_CMD0_CLR(_n1) (_n1)
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#define HW_SSP_CMD0_TOG(_n1) HW(SSP_CMD0_TOG(_n1))
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#define HWA_SSP_CMD0_TOG(_n1) (HWA_SSP_CMD0(_n1) + 0xc)
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#define HWT_SSP_CMD0_TOG(_n1) HWIO_32_WO
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#define HWN_SSP_CMD0_TOG(_n1) SSP_CMD0
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#define HWI_SSP_CMD0_TOG(_n1) (_n1)
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#define BP_SSP_CMD0_APPEND_8CYC 20
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#define BM_SSP_CMD0_APPEND_8CYC 0x100000
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#define BF_SSP_CMD0_APPEND_8CYC(v) (((v) & 0x1) << 20)
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#define BFM_SSP_CMD0_APPEND_8CYC(v) BM_SSP_CMD0_APPEND_8CYC
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#define BF_SSP_CMD0_APPEND_8CYC_V(e) BF_SSP_CMD0_APPEND_8CYC(BV_SSP_CMD0_APPEND_8CYC__##e)
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#define BFM_SSP_CMD0_APPEND_8CYC_V(v) BM_SSP_CMD0_APPEND_8CYC
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#define BP_SSP_CMD0_BLOCK_SIZE 16
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#define BM_SSP_CMD0_BLOCK_SIZE 0xf0000
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#define BF_SSP_CMD0_BLOCK_SIZE(v) (((v) & 0xf) << 16)
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#define BFM_SSP_CMD0_BLOCK_SIZE(v) BM_SSP_CMD0_BLOCK_SIZE
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#define BF_SSP_CMD0_BLOCK_SIZE_V(e) BF_SSP_CMD0_BLOCK_SIZE(BV_SSP_CMD0_BLOCK_SIZE__##e)
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#define BFM_SSP_CMD0_BLOCK_SIZE_V(v) BM_SSP_CMD0_BLOCK_SIZE
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#define BP_SSP_CMD0_BLOCK_COUNT 8
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#define BM_SSP_CMD0_BLOCK_COUNT 0xff00
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#define BF_SSP_CMD0_BLOCK_COUNT(v) (((v) & 0xff) << 8)
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#define BFM_SSP_CMD0_BLOCK_COUNT(v) BM_SSP_CMD0_BLOCK_COUNT
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#define BF_SSP_CMD0_BLOCK_COUNT_V(e) BF_SSP_CMD0_BLOCK_COUNT(BV_SSP_CMD0_BLOCK_COUNT__##e)
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#define BFM_SSP_CMD0_BLOCK_COUNT_V(v) BM_SSP_CMD0_BLOCK_COUNT
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#define BP_SSP_CMD0_CMD 0
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#define BM_SSP_CMD0_CMD 0xff
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#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x0
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#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x1
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#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x2
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#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x3
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#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x4
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#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x5
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#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x6
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#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x7
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#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x8
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#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x9
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#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0xa
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#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0xb
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#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0xc
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#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0xd
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#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0xe
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#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0xf
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#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10
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#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11
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#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12
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#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13
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#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14
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#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17
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#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18
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#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19
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#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1a
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#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1b
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#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1c
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#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1d
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#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1e
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#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23
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#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24
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#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26
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#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27
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#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28
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#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2a
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#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37
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#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38
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#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x0
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#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x2
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#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x3
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#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x4
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#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x5
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#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x7
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#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x9
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#define BV_SSP_CMD0_CMD__SD_SEND_CID 0xa
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#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0xc
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#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0xd
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#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0xf
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#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10
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#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11
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#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12
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#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18
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#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19
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#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1b
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#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1c
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#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1d
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#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1e
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#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20
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#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21
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#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23
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#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24
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#define BV_SSP_CMD0_CMD__SD_ERASE 0x26
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#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2a
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#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34
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#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35
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#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37
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#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38
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#define BF_SSP_CMD0_CMD(v) (((v) & 0xff) << 0)
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#define BFM_SSP_CMD0_CMD(v) BM_SSP_CMD0_CMD
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#define BF_SSP_CMD0_CMD_V(e) BF_SSP_CMD0_CMD(BV_SSP_CMD0_CMD__##e)
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#define BFM_SSP_CMD0_CMD_V(v) BM_SSP_CMD0_CMD
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#define HW_SSP_CMD1(_n1) HW(SSP_CMD1(_n1))
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#define HWA_SSP_CMD1(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x20)
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#define HWT_SSP_CMD1(_n1) HWIO_32_RW
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#define HWN_SSP_CMD1(_n1) SSP_CMD1
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#define HWI_SSP_CMD1(_n1) (_n1)
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#define BP_SSP_CMD1_CMD_ARG 0
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#define BM_SSP_CMD1_CMD_ARG 0xffffffff
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#define BF_SSP_CMD1_CMD_ARG(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_CMD1_CMD_ARG(v) BM_SSP_CMD1_CMD_ARG
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#define BF_SSP_CMD1_CMD_ARG_V(e) BF_SSP_CMD1_CMD_ARG(BV_SSP_CMD1_CMD_ARG__##e)
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#define BFM_SSP_CMD1_CMD_ARG_V(v) BM_SSP_CMD1_CMD_ARG
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#define HW_SSP_COMPREF(_n1) HW(SSP_COMPREF(_n1))
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#define HWA_SSP_COMPREF(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x30)
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#define HWT_SSP_COMPREF(_n1) HWIO_32_RW
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#define HWN_SSP_COMPREF(_n1) SSP_COMPREF
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#define HWI_SSP_COMPREF(_n1) (_n1)
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#define BP_SSP_COMPREF_REFERENCE 0
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#define BM_SSP_COMPREF_REFERENCE 0xffffffff
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#define BF_SSP_COMPREF_REFERENCE(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_COMPREF_REFERENCE(v) BM_SSP_COMPREF_REFERENCE
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#define BF_SSP_COMPREF_REFERENCE_V(e) BF_SSP_COMPREF_REFERENCE(BV_SSP_COMPREF_REFERENCE__##e)
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#define BFM_SSP_COMPREF_REFERENCE_V(v) BM_SSP_COMPREF_REFERENCE
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#define HW_SSP_COMPMASK(_n1) HW(SSP_COMPMASK(_n1))
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#define HWA_SSP_COMPMASK(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x40)
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#define HWT_SSP_COMPMASK(_n1) HWIO_32_RW
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#define HWN_SSP_COMPMASK(_n1) SSP_COMPMASK
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#define HWI_SSP_COMPMASK(_n1) (_n1)
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#define BP_SSP_COMPMASK_MASK 0
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#define BM_SSP_COMPMASK_MASK 0xffffffff
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#define BF_SSP_COMPMASK_MASK(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_COMPMASK_MASK(v) BM_SSP_COMPMASK_MASK
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#define BF_SSP_COMPMASK_MASK_V(e) BF_SSP_COMPMASK_MASK(BV_SSP_COMPMASK_MASK__##e)
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#define BFM_SSP_COMPMASK_MASK_V(v) BM_SSP_COMPMASK_MASK
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#define HW_SSP_TIMING(_n1) HW(SSP_TIMING(_n1))
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#define HWA_SSP_TIMING(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x50)
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#define HWT_SSP_TIMING(_n1) HWIO_32_RW
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#define HWN_SSP_TIMING(_n1) SSP_TIMING
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#define HWI_SSP_TIMING(_n1) (_n1)
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#define BP_SSP_TIMING_TIMEOUT 16
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#define BM_SSP_TIMING_TIMEOUT 0xffff0000
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#define BF_SSP_TIMING_TIMEOUT(v) (((v) & 0xffff) << 16)
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#define BFM_SSP_TIMING_TIMEOUT(v) BM_SSP_TIMING_TIMEOUT
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#define BF_SSP_TIMING_TIMEOUT_V(e) BF_SSP_TIMING_TIMEOUT(BV_SSP_TIMING_TIMEOUT__##e)
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#define BFM_SSP_TIMING_TIMEOUT_V(v) BM_SSP_TIMING_TIMEOUT
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#define BP_SSP_TIMING_CLOCK_DIVIDE 8
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#define BM_SSP_TIMING_CLOCK_DIVIDE 0xff00
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#define BF_SSP_TIMING_CLOCK_DIVIDE(v) (((v) & 0xff) << 8)
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#define BFM_SSP_TIMING_CLOCK_DIVIDE(v) BM_SSP_TIMING_CLOCK_DIVIDE
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#define BF_SSP_TIMING_CLOCK_DIVIDE_V(e) BF_SSP_TIMING_CLOCK_DIVIDE(BV_SSP_TIMING_CLOCK_DIVIDE__##e)
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#define BFM_SSP_TIMING_CLOCK_DIVIDE_V(v) BM_SSP_TIMING_CLOCK_DIVIDE
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#define BP_SSP_TIMING_CLOCK_RATE 0
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#define BM_SSP_TIMING_CLOCK_RATE 0xff
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#define BF_SSP_TIMING_CLOCK_RATE(v) (((v) & 0xff) << 0)
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#define BFM_SSP_TIMING_CLOCK_RATE(v) BM_SSP_TIMING_CLOCK_RATE
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#define BF_SSP_TIMING_CLOCK_RATE_V(e) BF_SSP_TIMING_CLOCK_RATE(BV_SSP_TIMING_CLOCK_RATE__##e)
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#define BFM_SSP_TIMING_CLOCK_RATE_V(v) BM_SSP_TIMING_CLOCK_RATE
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#define HW_SSP_CTRL1(_n1) HW(SSP_CTRL1(_n1))
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#define HWA_SSP_CTRL1(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x60)
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#define HWT_SSP_CTRL1(_n1) HWIO_32_RW
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#define HWN_SSP_CTRL1(_n1) SSP_CTRL1
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#define HWI_SSP_CTRL1(_n1) (_n1)
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#define HW_SSP_CTRL1_SET(_n1) HW(SSP_CTRL1_SET(_n1))
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#define HWA_SSP_CTRL1_SET(_n1) (HWA_SSP_CTRL1(_n1) + 0x4)
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#define HWT_SSP_CTRL1_SET(_n1) HWIO_32_WO
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#define HWN_SSP_CTRL1_SET(_n1) SSP_CTRL1
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#define HWI_SSP_CTRL1_SET(_n1) (_n1)
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#define HW_SSP_CTRL1_CLR(_n1) HW(SSP_CTRL1_CLR(_n1))
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#define HWA_SSP_CTRL1_CLR(_n1) (HWA_SSP_CTRL1(_n1) + 0x8)
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#define HWT_SSP_CTRL1_CLR(_n1) HWIO_32_WO
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#define HWN_SSP_CTRL1_CLR(_n1) SSP_CTRL1
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#define HWI_SSP_CTRL1_CLR(_n1) (_n1)
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#define HW_SSP_CTRL1_TOG(_n1) HW(SSP_CTRL1_TOG(_n1))
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#define HWA_SSP_CTRL1_TOG(_n1) (HWA_SSP_CTRL1(_n1) + 0xc)
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#define HWT_SSP_CTRL1_TOG(_n1) HWIO_32_WO
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#define HWN_SSP_CTRL1_TOG(_n1) SSP_CTRL1
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#define HWI_SSP_CTRL1_TOG(_n1) (_n1)
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#define BP_SSP_CTRL1_SDIO_IRQ 31
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#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
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#define BF_SSP_CTRL1_SDIO_IRQ(v) (((v) & 0x1) << 31)
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#define BFM_SSP_CTRL1_SDIO_IRQ(v) BM_SSP_CTRL1_SDIO_IRQ
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#define BF_SSP_CTRL1_SDIO_IRQ_V(e) BF_SSP_CTRL1_SDIO_IRQ(BV_SSP_CTRL1_SDIO_IRQ__##e)
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#define BFM_SSP_CTRL1_SDIO_IRQ_V(v) BM_SSP_CTRL1_SDIO_IRQ
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#define BP_SSP_CTRL1_SDIO_IRQ_EN 30
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#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000
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#define BF_SSP_CTRL1_SDIO_IRQ_EN(v) (((v) & 0x1) << 30)
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#define BFM_SSP_CTRL1_SDIO_IRQ_EN(v) BM_SSP_CTRL1_SDIO_IRQ_EN
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#define BF_SSP_CTRL1_SDIO_IRQ_EN_V(e) BF_SSP_CTRL1_SDIO_IRQ_EN(BV_SSP_CTRL1_SDIO_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_SDIO_IRQ_EN_V(v) BM_SSP_CTRL1_SDIO_IRQ_EN
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#define BP_SSP_CTRL1_RESP_ERR_IRQ 29
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#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
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#define BF_SSP_CTRL1_RESP_ERR_IRQ(v) (((v) & 0x1) << 29)
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#define BFM_SSP_CTRL1_RESP_ERR_IRQ(v) BM_SSP_CTRL1_RESP_ERR_IRQ
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#define BF_SSP_CTRL1_RESP_ERR_IRQ_V(e) BF_SSP_CTRL1_RESP_ERR_IRQ(BV_SSP_CTRL1_RESP_ERR_IRQ__##e)
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#define BFM_SSP_CTRL1_RESP_ERR_IRQ_V(v) BM_SSP_CTRL1_RESP_ERR_IRQ
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#define BP_SSP_CTRL1_RESP_ERR_IRQ_EN 28
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#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
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#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN(v) (((v) & 0x1) << 28)
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#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN(v) BM_SSP_CTRL1_RESP_ERR_IRQ_EN
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#define BF_SSP_CTRL1_RESP_ERR_IRQ_EN_V(e) BF_SSP_CTRL1_RESP_ERR_IRQ_EN(BV_SSP_CTRL1_RESP_ERR_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_RESP_ERR_IRQ_EN_V(v) BM_SSP_CTRL1_RESP_ERR_IRQ_EN
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#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ 27
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x8000000
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#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(v) (((v) & 0x1) << 27)
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#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ(v) BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
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#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(e) BF_SSP_CTRL1_RESP_TIMEOUT_IRQ(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ__##e)
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#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_V(v) BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
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#define BP_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 26
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x4000000
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#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v) (((v) & 0x1) << 26)
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#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(v) BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
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#define BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(e) BF_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN_V(v) BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
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#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ 25
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x2000000
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#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(v) (((v) & 0x1) << 25)
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#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ(v) BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
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#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(e) BF_SSP_CTRL1_DATA_TIMEOUT_IRQ(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ__##e)
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#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_V(v) BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
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#define BP_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 24
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x1000000
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#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v) (((v) & 0x1) << 24)
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#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(v) BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
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#define BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(e) BF_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN_V(v) BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
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#define BP_SSP_CTRL1_DATA_CRC_IRQ 23
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#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x800000
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#define BF_SSP_CTRL1_DATA_CRC_IRQ(v) (((v) & 0x1) << 23)
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#define BFM_SSP_CTRL1_DATA_CRC_IRQ(v) BM_SSP_CTRL1_DATA_CRC_IRQ
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#define BF_SSP_CTRL1_DATA_CRC_IRQ_V(e) BF_SSP_CTRL1_DATA_CRC_IRQ(BV_SSP_CTRL1_DATA_CRC_IRQ__##e)
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#define BFM_SSP_CTRL1_DATA_CRC_IRQ_V(v) BM_SSP_CTRL1_DATA_CRC_IRQ
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#define BP_SSP_CTRL1_DATA_CRC_IRQ_EN 22
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#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x400000
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#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN(v) (((v) & 0x1) << 22)
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#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN(v) BM_SSP_CTRL1_DATA_CRC_IRQ_EN
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#define BF_SSP_CTRL1_DATA_CRC_IRQ_EN_V(e) BF_SSP_CTRL1_DATA_CRC_IRQ_EN(BV_SSP_CTRL1_DATA_CRC_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_DATA_CRC_IRQ_EN_V(v) BM_SSP_CTRL1_DATA_CRC_IRQ_EN
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#define BP_SSP_CTRL1_FIFO_UNDERRUN_IRQ 21
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#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x200000
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#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v) (((v) & 0x1) << 21)
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#define BFM_SSP_CTRL1_FIFO_UNDERRUN_IRQ(v) BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
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#define BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ_V(e) BF_SSP_CTRL1_FIFO_UNDERRUN_IRQ(BV_SSP_CTRL1_FIFO_UNDERRUN_IRQ__##e)
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#define BFM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_V(v) BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
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#define BP_SSP_CTRL1_FIFO_UNDERRUN_EN 20
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#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x100000
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#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN(v) (((v) & 0x1) << 20)
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#define BFM_SSP_CTRL1_FIFO_UNDERRUN_EN(v) BM_SSP_CTRL1_FIFO_UNDERRUN_EN
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#define BF_SSP_CTRL1_FIFO_UNDERRUN_EN_V(e) BF_SSP_CTRL1_FIFO_UNDERRUN_EN(BV_SSP_CTRL1_FIFO_UNDERRUN_EN__##e)
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#define BFM_SSP_CTRL1_FIFO_UNDERRUN_EN_V(v) BM_SSP_CTRL1_FIFO_UNDERRUN_EN
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#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ 19
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#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x80000
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#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v) (((v) & 0x1) << 19)
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#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ(v) BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ
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#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_V(e) BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ(BV_SSP_CTRL1_CEATA_CCS_ERR_IRQ__##e)
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#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_V(v) BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ
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#define BP_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 18
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#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x40000
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#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v) (((v) & 0x1) << 18)
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#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(v) BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN
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#define BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN_V(e) BF_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN(BV_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN_V(v) BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN
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#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ 17
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x20000
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#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(v) (((v) & 0x1) << 17)
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#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ(v) BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
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#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(e) BF_SSP_CTRL1_RECV_TIMEOUT_IRQ(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ__##e)
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#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_V(v) BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
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#define BP_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 16
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x10000
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#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v) (((v) & 0x1) << 16)
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#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(v) BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
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#define BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(e) BF_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN(BV_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN_V(v) BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
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#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ 15
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#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x8000
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#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(v) (((v) & 0x1) << 15)
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#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ(v) BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
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#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_V(e) BF_SSP_CTRL1_FIFO_OVERRUN_IRQ(BV_SSP_CTRL1_FIFO_OVERRUN_IRQ__##e)
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#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_V(v) BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
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#define BP_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 14
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#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x4000
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#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v) (((v) & 0x1) << 14)
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#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(v) BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
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#define BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN_V(e) BF_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN(BV_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN__##e)
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#define BFM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN_V(v) BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
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#define BP_SSP_CTRL1_DMA_ENABLE 13
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#define BM_SSP_CTRL1_DMA_ENABLE 0x2000
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#define BF_SSP_CTRL1_DMA_ENABLE(v) (((v) & 0x1) << 13)
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#define BFM_SSP_CTRL1_DMA_ENABLE(v) BM_SSP_CTRL1_DMA_ENABLE
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#define BF_SSP_CTRL1_DMA_ENABLE_V(e) BF_SSP_CTRL1_DMA_ENABLE(BV_SSP_CTRL1_DMA_ENABLE__##e)
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#define BFM_SSP_CTRL1_DMA_ENABLE_V(v) BM_SSP_CTRL1_DMA_ENABLE
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#define BP_SSP_CTRL1_CEATA_CCS_ERR_EN 12
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#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x1000
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#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN(v) (((v) & 0x1) << 12)
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#define BFM_SSP_CTRL1_CEATA_CCS_ERR_EN(v) BM_SSP_CTRL1_CEATA_CCS_ERR_EN
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#define BF_SSP_CTRL1_CEATA_CCS_ERR_EN_V(e) BF_SSP_CTRL1_CEATA_CCS_ERR_EN(BV_SSP_CTRL1_CEATA_CCS_ERR_EN__##e)
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#define BFM_SSP_CTRL1_CEATA_CCS_ERR_EN_V(v) BM_SSP_CTRL1_CEATA_CCS_ERR_EN
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#define BP_SSP_CTRL1_SLAVE_OUT_DISABLE 11
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#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x800
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#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE(v) (((v) & 0x1) << 11)
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#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE(v) BM_SSP_CTRL1_SLAVE_OUT_DISABLE
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#define BF_SSP_CTRL1_SLAVE_OUT_DISABLE_V(e) BF_SSP_CTRL1_SLAVE_OUT_DISABLE(BV_SSP_CTRL1_SLAVE_OUT_DISABLE__##e)
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#define BFM_SSP_CTRL1_SLAVE_OUT_DISABLE_V(v) BM_SSP_CTRL1_SLAVE_OUT_DISABLE
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#define BP_SSP_CTRL1_PHASE 10
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#define BM_SSP_CTRL1_PHASE 0x400
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#define BF_SSP_CTRL1_PHASE(v) (((v) & 0x1) << 10)
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#define BFM_SSP_CTRL1_PHASE(v) BM_SSP_CTRL1_PHASE
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#define BF_SSP_CTRL1_PHASE_V(e) BF_SSP_CTRL1_PHASE(BV_SSP_CTRL1_PHASE__##e)
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#define BFM_SSP_CTRL1_PHASE_V(v) BM_SSP_CTRL1_PHASE
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#define BP_SSP_CTRL1_POLARITY 9
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#define BM_SSP_CTRL1_POLARITY 0x200
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#define BF_SSP_CTRL1_POLARITY(v) (((v) & 0x1) << 9)
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#define BFM_SSP_CTRL1_POLARITY(v) BM_SSP_CTRL1_POLARITY
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#define BF_SSP_CTRL1_POLARITY_V(e) BF_SSP_CTRL1_POLARITY(BV_SSP_CTRL1_POLARITY__##e)
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#define BFM_SSP_CTRL1_POLARITY_V(v) BM_SSP_CTRL1_POLARITY
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#define BP_SSP_CTRL1_SLAVE_MODE 8
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#define BM_SSP_CTRL1_SLAVE_MODE 0x100
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#define BF_SSP_CTRL1_SLAVE_MODE(v) (((v) & 0x1) << 8)
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#define BFM_SSP_CTRL1_SLAVE_MODE(v) BM_SSP_CTRL1_SLAVE_MODE
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#define BF_SSP_CTRL1_SLAVE_MODE_V(e) BF_SSP_CTRL1_SLAVE_MODE(BV_SSP_CTRL1_SLAVE_MODE__##e)
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#define BFM_SSP_CTRL1_SLAVE_MODE_V(v) BM_SSP_CTRL1_SLAVE_MODE
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#define BP_SSP_CTRL1_WORD_LENGTH 4
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#define BM_SSP_CTRL1_WORD_LENGTH 0xf0
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#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0
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#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1
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#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2
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#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
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#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
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#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xf
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#define BF_SSP_CTRL1_WORD_LENGTH(v) (((v) & 0xf) << 4)
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#define BFM_SSP_CTRL1_WORD_LENGTH(v) BM_SSP_CTRL1_WORD_LENGTH
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#define BF_SSP_CTRL1_WORD_LENGTH_V(e) BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__##e)
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#define BFM_SSP_CTRL1_WORD_LENGTH_V(v) BM_SSP_CTRL1_WORD_LENGTH
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#define BP_SSP_CTRL1_SSP_MODE 0
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#define BM_SSP_CTRL1_SSP_MODE 0xf
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#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
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#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
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#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
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#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
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#define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7
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#define BF_SSP_CTRL1_SSP_MODE(v) (((v) & 0xf) << 0)
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#define BFM_SSP_CTRL1_SSP_MODE(v) BM_SSP_CTRL1_SSP_MODE
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#define BF_SSP_CTRL1_SSP_MODE_V(e) BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__##e)
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#define BFM_SSP_CTRL1_SSP_MODE_V(v) BM_SSP_CTRL1_SSP_MODE
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#define HW_SSP_DATA(_n1) HW(SSP_DATA(_n1))
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#define HWA_SSP_DATA(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x70)
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#define HWT_SSP_DATA(_n1) HWIO_32_RW
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#define HWN_SSP_DATA(_n1) SSP_DATA
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#define HWI_SSP_DATA(_n1) (_n1)
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#define BP_SSP_DATA_DATA 0
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#define BM_SSP_DATA_DATA 0xffffffff
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#define BF_SSP_DATA_DATA(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_DATA_DATA(v) BM_SSP_DATA_DATA
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#define BF_SSP_DATA_DATA_V(e) BF_SSP_DATA_DATA(BV_SSP_DATA_DATA__##e)
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#define BFM_SSP_DATA_DATA_V(v) BM_SSP_DATA_DATA
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#define HW_SSP_SDRESP0(_n1) HW(SSP_SDRESP0(_n1))
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#define HWA_SSP_SDRESP0(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x80)
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#define HWT_SSP_SDRESP0(_n1) HWIO_32_RW
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#define HWN_SSP_SDRESP0(_n1) SSP_SDRESP0
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#define HWI_SSP_SDRESP0(_n1) (_n1)
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#define BP_SSP_SDRESP0_RESP0 0
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#define BM_SSP_SDRESP0_RESP0 0xffffffff
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#define BF_SSP_SDRESP0_RESP0(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_SDRESP0_RESP0(v) BM_SSP_SDRESP0_RESP0
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#define BF_SSP_SDRESP0_RESP0_V(e) BF_SSP_SDRESP0_RESP0(BV_SSP_SDRESP0_RESP0__##e)
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#define BFM_SSP_SDRESP0_RESP0_V(v) BM_SSP_SDRESP0_RESP0
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#define HW_SSP_SDRESP1(_n1) HW(SSP_SDRESP1(_n1))
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#define HWA_SSP_SDRESP1(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x90)
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#define HWT_SSP_SDRESP1(_n1) HWIO_32_RW
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#define HWN_SSP_SDRESP1(_n1) SSP_SDRESP1
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#define HWI_SSP_SDRESP1(_n1) (_n1)
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#define BP_SSP_SDRESP1_RESP1 0
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#define BM_SSP_SDRESP1_RESP1 0xffffffff
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#define BF_SSP_SDRESP1_RESP1(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_SDRESP1_RESP1(v) BM_SSP_SDRESP1_RESP1
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#define BF_SSP_SDRESP1_RESP1_V(e) BF_SSP_SDRESP1_RESP1(BV_SSP_SDRESP1_RESP1__##e)
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#define BFM_SSP_SDRESP1_RESP1_V(v) BM_SSP_SDRESP1_RESP1
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#define HW_SSP_SDRESP2(_n1) HW(SSP_SDRESP2(_n1))
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#define HWA_SSP_SDRESP2(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xa0)
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#define HWT_SSP_SDRESP2(_n1) HWIO_32_RW
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#define HWN_SSP_SDRESP2(_n1) SSP_SDRESP2
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#define HWI_SSP_SDRESP2(_n1) (_n1)
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#define BP_SSP_SDRESP2_RESP2 0
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#define BM_SSP_SDRESP2_RESP2 0xffffffff
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#define BF_SSP_SDRESP2_RESP2(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_SDRESP2_RESP2(v) BM_SSP_SDRESP2_RESP2
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#define BF_SSP_SDRESP2_RESP2_V(e) BF_SSP_SDRESP2_RESP2(BV_SSP_SDRESP2_RESP2__##e)
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#define BFM_SSP_SDRESP2_RESP2_V(v) BM_SSP_SDRESP2_RESP2
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#define HW_SSP_SDRESP3(_n1) HW(SSP_SDRESP3(_n1))
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#define HWA_SSP_SDRESP3(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xb0)
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#define HWT_SSP_SDRESP3(_n1) HWIO_32_RW
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#define HWN_SSP_SDRESP3(_n1) SSP_SDRESP3
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#define HWI_SSP_SDRESP3(_n1) (_n1)
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#define BP_SSP_SDRESP3_RESP3 0
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#define BM_SSP_SDRESP3_RESP3 0xffffffff
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#define BF_SSP_SDRESP3_RESP3(v) (((v) & 0xffffffff) << 0)
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#define BFM_SSP_SDRESP3_RESP3(v) BM_SSP_SDRESP3_RESP3
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#define BF_SSP_SDRESP3_RESP3_V(e) BF_SSP_SDRESP3_RESP3(BV_SSP_SDRESP3_RESP3__##e)
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#define BFM_SSP_SDRESP3_RESP3_V(v) BM_SSP_SDRESP3_RESP3
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#define HW_SSP_STATUS(_n1) HW(SSP_STATUS(_n1))
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#define HWA_SSP_STATUS(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0xc0)
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#define HWT_SSP_STATUS(_n1) HWIO_32_RW
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#define HWN_SSP_STATUS(_n1) SSP_STATUS
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#define HWI_SSP_STATUS(_n1) (_n1)
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#define BP_SSP_STATUS_PRESENT 31
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#define BM_SSP_STATUS_PRESENT 0x80000000
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#define BF_SSP_STATUS_PRESENT(v) (((v) & 0x1) << 31)
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#define BFM_SSP_STATUS_PRESENT(v) BM_SSP_STATUS_PRESENT
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#define BF_SSP_STATUS_PRESENT_V(e) BF_SSP_STATUS_PRESENT(BV_SSP_STATUS_PRESENT__##e)
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#define BFM_SSP_STATUS_PRESENT_V(v) BM_SSP_STATUS_PRESENT
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#define BP_SSP_STATUS_MS_PRESENT 30
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#define BM_SSP_STATUS_MS_PRESENT 0x40000000
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#define BF_SSP_STATUS_MS_PRESENT(v) (((v) & 0x1) << 30)
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#define BFM_SSP_STATUS_MS_PRESENT(v) BM_SSP_STATUS_MS_PRESENT
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#define BF_SSP_STATUS_MS_PRESENT_V(e) BF_SSP_STATUS_MS_PRESENT(BV_SSP_STATUS_MS_PRESENT__##e)
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#define BFM_SSP_STATUS_MS_PRESENT_V(v) BM_SSP_STATUS_MS_PRESENT
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#define BP_SSP_STATUS_SD_PRESENT 29
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#define BM_SSP_STATUS_SD_PRESENT 0x20000000
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#define BF_SSP_STATUS_SD_PRESENT(v) (((v) & 0x1) << 29)
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#define BFM_SSP_STATUS_SD_PRESENT(v) BM_SSP_STATUS_SD_PRESENT
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#define BF_SSP_STATUS_SD_PRESENT_V(e) BF_SSP_STATUS_SD_PRESENT(BV_SSP_STATUS_SD_PRESENT__##e)
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#define BFM_SSP_STATUS_SD_PRESENT_V(v) BM_SSP_STATUS_SD_PRESENT
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#define BP_SSP_STATUS_CARD_DETECT 28
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#define BM_SSP_STATUS_CARD_DETECT 0x10000000
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#define BF_SSP_STATUS_CARD_DETECT(v) (((v) & 0x1) << 28)
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#define BFM_SSP_STATUS_CARD_DETECT(v) BM_SSP_STATUS_CARD_DETECT
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#define BF_SSP_STATUS_CARD_DETECT_V(e) BF_SSP_STATUS_CARD_DETECT(BV_SSP_STATUS_CARD_DETECT__##e)
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#define BFM_SSP_STATUS_CARD_DETECT_V(v) BM_SSP_STATUS_CARD_DETECT
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#define BP_SSP_STATUS_DMASENSE 21
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#define BM_SSP_STATUS_DMASENSE 0x200000
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#define BF_SSP_STATUS_DMASENSE(v) (((v) & 0x1) << 21)
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#define BFM_SSP_STATUS_DMASENSE(v) BM_SSP_STATUS_DMASENSE
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#define BF_SSP_STATUS_DMASENSE_V(e) BF_SSP_STATUS_DMASENSE(BV_SSP_STATUS_DMASENSE__##e)
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#define BFM_SSP_STATUS_DMASENSE_V(v) BM_SSP_STATUS_DMASENSE
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#define BP_SSP_STATUS_DMATERM 20
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#define BM_SSP_STATUS_DMATERM 0x100000
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#define BF_SSP_STATUS_DMATERM(v) (((v) & 0x1) << 20)
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#define BFM_SSP_STATUS_DMATERM(v) BM_SSP_STATUS_DMATERM
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#define BF_SSP_STATUS_DMATERM_V(e) BF_SSP_STATUS_DMATERM(BV_SSP_STATUS_DMATERM__##e)
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#define BFM_SSP_STATUS_DMATERM_V(v) BM_SSP_STATUS_DMATERM
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#define BP_SSP_STATUS_DMAREQ 19
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#define BM_SSP_STATUS_DMAREQ 0x80000
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#define BF_SSP_STATUS_DMAREQ(v) (((v) & 0x1) << 19)
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#define BFM_SSP_STATUS_DMAREQ(v) BM_SSP_STATUS_DMAREQ
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#define BF_SSP_STATUS_DMAREQ_V(e) BF_SSP_STATUS_DMAREQ(BV_SSP_STATUS_DMAREQ__##e)
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#define BFM_SSP_STATUS_DMAREQ_V(v) BM_SSP_STATUS_DMAREQ
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#define BP_SSP_STATUS_DMAEND 18
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#define BM_SSP_STATUS_DMAEND 0x40000
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#define BF_SSP_STATUS_DMAEND(v) (((v) & 0x1) << 18)
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#define BFM_SSP_STATUS_DMAEND(v) BM_SSP_STATUS_DMAEND
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#define BF_SSP_STATUS_DMAEND_V(e) BF_SSP_STATUS_DMAEND(BV_SSP_STATUS_DMAEND__##e)
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#define BFM_SSP_STATUS_DMAEND_V(v) BM_SSP_STATUS_DMAEND
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#define BP_SSP_STATUS_SDIO_IRQ 17
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#define BM_SSP_STATUS_SDIO_IRQ 0x20000
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#define BF_SSP_STATUS_SDIO_IRQ(v) (((v) & 0x1) << 17)
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#define BFM_SSP_STATUS_SDIO_IRQ(v) BM_SSP_STATUS_SDIO_IRQ
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#define BF_SSP_STATUS_SDIO_IRQ_V(e) BF_SSP_STATUS_SDIO_IRQ(BV_SSP_STATUS_SDIO_IRQ__##e)
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#define BFM_SSP_STATUS_SDIO_IRQ_V(v) BM_SSP_STATUS_SDIO_IRQ
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#define BP_SSP_STATUS_RESP_CRC_ERR 16
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#define BM_SSP_STATUS_RESP_CRC_ERR 0x10000
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#define BF_SSP_STATUS_RESP_CRC_ERR(v) (((v) & 0x1) << 16)
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#define BFM_SSP_STATUS_RESP_CRC_ERR(v) BM_SSP_STATUS_RESP_CRC_ERR
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#define BF_SSP_STATUS_RESP_CRC_ERR_V(e) BF_SSP_STATUS_RESP_CRC_ERR(BV_SSP_STATUS_RESP_CRC_ERR__##e)
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#define BFM_SSP_STATUS_RESP_CRC_ERR_V(v) BM_SSP_STATUS_RESP_CRC_ERR
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#define BP_SSP_STATUS_RESP_ERR 15
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#define BM_SSP_STATUS_RESP_ERR 0x8000
|
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#define BF_SSP_STATUS_RESP_ERR(v) (((v) & 0x1) << 15)
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#define BFM_SSP_STATUS_RESP_ERR(v) BM_SSP_STATUS_RESP_ERR
|
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#define BF_SSP_STATUS_RESP_ERR_V(e) BF_SSP_STATUS_RESP_ERR(BV_SSP_STATUS_RESP_ERR__##e)
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#define BFM_SSP_STATUS_RESP_ERR_V(v) BM_SSP_STATUS_RESP_ERR
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#define BP_SSP_STATUS_RESP_TIMEOUT 14
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#define BM_SSP_STATUS_RESP_TIMEOUT 0x4000
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#define BF_SSP_STATUS_RESP_TIMEOUT(v) (((v) & 0x1) << 14)
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#define BFM_SSP_STATUS_RESP_TIMEOUT(v) BM_SSP_STATUS_RESP_TIMEOUT
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#define BF_SSP_STATUS_RESP_TIMEOUT_V(e) BF_SSP_STATUS_RESP_TIMEOUT(BV_SSP_STATUS_RESP_TIMEOUT__##e)
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#define BFM_SSP_STATUS_RESP_TIMEOUT_V(v) BM_SSP_STATUS_RESP_TIMEOUT
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#define BP_SSP_STATUS_DATA_CRC_ERR 13
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#define BM_SSP_STATUS_DATA_CRC_ERR 0x2000
|
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#define BF_SSP_STATUS_DATA_CRC_ERR(v) (((v) & 0x1) << 13)
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#define BFM_SSP_STATUS_DATA_CRC_ERR(v) BM_SSP_STATUS_DATA_CRC_ERR
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#define BF_SSP_STATUS_DATA_CRC_ERR_V(e) BF_SSP_STATUS_DATA_CRC_ERR(BV_SSP_STATUS_DATA_CRC_ERR__##e)
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#define BFM_SSP_STATUS_DATA_CRC_ERR_V(v) BM_SSP_STATUS_DATA_CRC_ERR
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#define BP_SSP_STATUS_TIMEOUT 12
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#define BM_SSP_STATUS_TIMEOUT 0x1000
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#define BF_SSP_STATUS_TIMEOUT(v) (((v) & 0x1) << 12)
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#define BFM_SSP_STATUS_TIMEOUT(v) BM_SSP_STATUS_TIMEOUT
|
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#define BF_SSP_STATUS_TIMEOUT_V(e) BF_SSP_STATUS_TIMEOUT(BV_SSP_STATUS_TIMEOUT__##e)
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#define BFM_SSP_STATUS_TIMEOUT_V(v) BM_SSP_STATUS_TIMEOUT
|
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#define BP_SSP_STATUS_RECV_TIMEOUT_STAT 11
|
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#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x800
|
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#define BF_SSP_STATUS_RECV_TIMEOUT_STAT(v) (((v) & 0x1) << 11)
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#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT(v) BM_SSP_STATUS_RECV_TIMEOUT_STAT
|
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#define BF_SSP_STATUS_RECV_TIMEOUT_STAT_V(e) BF_SSP_STATUS_RECV_TIMEOUT_STAT(BV_SSP_STATUS_RECV_TIMEOUT_STAT__##e)
|
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#define BFM_SSP_STATUS_RECV_TIMEOUT_STAT_V(v) BM_SSP_STATUS_RECV_TIMEOUT_STAT
|
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#define BP_SSP_STATUS_CEATA_CCS_ERR 10
|
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#define BM_SSP_STATUS_CEATA_CCS_ERR 0x400
|
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#define BF_SSP_STATUS_CEATA_CCS_ERR(v) (((v) & 0x1) << 10)
|
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#define BFM_SSP_STATUS_CEATA_CCS_ERR(v) BM_SSP_STATUS_CEATA_CCS_ERR
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#define BF_SSP_STATUS_CEATA_CCS_ERR_V(e) BF_SSP_STATUS_CEATA_CCS_ERR(BV_SSP_STATUS_CEATA_CCS_ERR__##e)
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#define BFM_SSP_STATUS_CEATA_CCS_ERR_V(v) BM_SSP_STATUS_CEATA_CCS_ERR
|
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#define BP_SSP_STATUS_FIFO_OVRFLW 9
|
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#define BM_SSP_STATUS_FIFO_OVRFLW 0x200
|
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#define BF_SSP_STATUS_FIFO_OVRFLW(v) (((v) & 0x1) << 9)
|
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#define BFM_SSP_STATUS_FIFO_OVRFLW(v) BM_SSP_STATUS_FIFO_OVRFLW
|
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#define BF_SSP_STATUS_FIFO_OVRFLW_V(e) BF_SSP_STATUS_FIFO_OVRFLW(BV_SSP_STATUS_FIFO_OVRFLW__##e)
|
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#define BFM_SSP_STATUS_FIFO_OVRFLW_V(v) BM_SSP_STATUS_FIFO_OVRFLW
|
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#define BP_SSP_STATUS_FIFO_FULL 8
|
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#define BM_SSP_STATUS_FIFO_FULL 0x100
|
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#define BF_SSP_STATUS_FIFO_FULL(v) (((v) & 0x1) << 8)
|
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#define BFM_SSP_STATUS_FIFO_FULL(v) BM_SSP_STATUS_FIFO_FULL
|
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#define BF_SSP_STATUS_FIFO_FULL_V(e) BF_SSP_STATUS_FIFO_FULL(BV_SSP_STATUS_FIFO_FULL__##e)
|
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#define BFM_SSP_STATUS_FIFO_FULL_V(v) BM_SSP_STATUS_FIFO_FULL
|
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#define BP_SSP_STATUS_FIFO_EMPTY 5
|
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#define BM_SSP_STATUS_FIFO_EMPTY 0x20
|
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#define BF_SSP_STATUS_FIFO_EMPTY(v) (((v) & 0x1) << 5)
|
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#define BFM_SSP_STATUS_FIFO_EMPTY(v) BM_SSP_STATUS_FIFO_EMPTY
|
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#define BF_SSP_STATUS_FIFO_EMPTY_V(e) BF_SSP_STATUS_FIFO_EMPTY(BV_SSP_STATUS_FIFO_EMPTY__##e)
|
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#define BFM_SSP_STATUS_FIFO_EMPTY_V(v) BM_SSP_STATUS_FIFO_EMPTY
|
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#define BP_SSP_STATUS_FIFO_UNDRFLW 4
|
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#define BM_SSP_STATUS_FIFO_UNDRFLW 0x10
|
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#define BF_SSP_STATUS_FIFO_UNDRFLW(v) (((v) & 0x1) << 4)
|
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#define BFM_SSP_STATUS_FIFO_UNDRFLW(v) BM_SSP_STATUS_FIFO_UNDRFLW
|
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#define BF_SSP_STATUS_FIFO_UNDRFLW_V(e) BF_SSP_STATUS_FIFO_UNDRFLW(BV_SSP_STATUS_FIFO_UNDRFLW__##e)
|
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#define BFM_SSP_STATUS_FIFO_UNDRFLW_V(v) BM_SSP_STATUS_FIFO_UNDRFLW
|
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#define BP_SSP_STATUS_CMD_BUSY 3
|
|
#define BM_SSP_STATUS_CMD_BUSY 0x8
|
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#define BF_SSP_STATUS_CMD_BUSY(v) (((v) & 0x1) << 3)
|
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#define BFM_SSP_STATUS_CMD_BUSY(v) BM_SSP_STATUS_CMD_BUSY
|
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#define BF_SSP_STATUS_CMD_BUSY_V(e) BF_SSP_STATUS_CMD_BUSY(BV_SSP_STATUS_CMD_BUSY__##e)
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#define BFM_SSP_STATUS_CMD_BUSY_V(v) BM_SSP_STATUS_CMD_BUSY
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#define BP_SSP_STATUS_DATA_BUSY 2
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#define BM_SSP_STATUS_DATA_BUSY 0x4
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#define BF_SSP_STATUS_DATA_BUSY(v) (((v) & 0x1) << 2)
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#define BFM_SSP_STATUS_DATA_BUSY(v) BM_SSP_STATUS_DATA_BUSY
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#define BF_SSP_STATUS_DATA_BUSY_V(e) BF_SSP_STATUS_DATA_BUSY(BV_SSP_STATUS_DATA_BUSY__##e)
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#define BFM_SSP_STATUS_DATA_BUSY_V(v) BM_SSP_STATUS_DATA_BUSY
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#define BP_SSP_STATUS_BUSY 0
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#define BM_SSP_STATUS_BUSY 0x1
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#define BF_SSP_STATUS_BUSY(v) (((v) & 0x1) << 0)
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#define BFM_SSP_STATUS_BUSY(v) BM_SSP_STATUS_BUSY
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#define BF_SSP_STATUS_BUSY_V(e) BF_SSP_STATUS_BUSY(BV_SSP_STATUS_BUSY__##e)
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#define BFM_SSP_STATUS_BUSY_V(v) BM_SSP_STATUS_BUSY
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#define HW_SSP_DEBUG(_n1) HW(SSP_DEBUG(_n1))
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#define HWA_SSP_DEBUG(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x100)
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#define HWT_SSP_DEBUG(_n1) HWIO_32_RW
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#define HWN_SSP_DEBUG(_n1) SSP_DEBUG
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#define HWI_SSP_DEBUG(_n1) (_n1)
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#define BP_SSP_DEBUG_DATACRC_ERR 28
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#define BM_SSP_DEBUG_DATACRC_ERR 0xf0000000
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#define BF_SSP_DEBUG_DATACRC_ERR(v) (((v) & 0xf) << 28)
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#define BFM_SSP_DEBUG_DATACRC_ERR(v) BM_SSP_DEBUG_DATACRC_ERR
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#define BF_SSP_DEBUG_DATACRC_ERR_V(e) BF_SSP_DEBUG_DATACRC_ERR(BV_SSP_DEBUG_DATACRC_ERR__##e)
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#define BFM_SSP_DEBUG_DATACRC_ERR_V(v) BM_SSP_DEBUG_DATACRC_ERR
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#define BP_SSP_DEBUG_DATA_STALL 27
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#define BM_SSP_DEBUG_DATA_STALL 0x8000000
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#define BF_SSP_DEBUG_DATA_STALL(v) (((v) & 0x1) << 27)
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#define BFM_SSP_DEBUG_DATA_STALL(v) BM_SSP_DEBUG_DATA_STALL
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#define BF_SSP_DEBUG_DATA_STALL_V(e) BF_SSP_DEBUG_DATA_STALL(BV_SSP_DEBUG_DATA_STALL__##e)
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#define BFM_SSP_DEBUG_DATA_STALL_V(v) BM_SSP_DEBUG_DATA_STALL
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#define BP_SSP_DEBUG_DAT_SM 24
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#define BM_SSP_DEBUG_DAT_SM 0x7000000
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#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0
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#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2
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#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3
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#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4
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#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5
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#define BF_SSP_DEBUG_DAT_SM(v) (((v) & 0x7) << 24)
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#define BFM_SSP_DEBUG_DAT_SM(v) BM_SSP_DEBUG_DAT_SM
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#define BF_SSP_DEBUG_DAT_SM_V(e) BF_SSP_DEBUG_DAT_SM(BV_SSP_DEBUG_DAT_SM__##e)
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#define BFM_SSP_DEBUG_DAT_SM_V(v) BM_SSP_DEBUG_DAT_SM
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#define BP_SSP_DEBUG_MSTK_SM 20
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#define BM_SSP_DEBUG_MSTK_SM 0xf00000
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xa
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xb
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xc
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xd
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#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xe
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#define BF_SSP_DEBUG_MSTK_SM(v) (((v) & 0xf) << 20)
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#define BFM_SSP_DEBUG_MSTK_SM(v) BM_SSP_DEBUG_MSTK_SM
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#define BF_SSP_DEBUG_MSTK_SM_V(e) BF_SSP_DEBUG_MSTK_SM(BV_SSP_DEBUG_MSTK_SM__##e)
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#define BFM_SSP_DEBUG_MSTK_SM_V(v) BM_SSP_DEBUG_MSTK_SM
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#define BP_SSP_DEBUG_CMD_OE 19
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#define BM_SSP_DEBUG_CMD_OE 0x80000
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#define BF_SSP_DEBUG_CMD_OE(v) (((v) & 0x1) << 19)
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#define BFM_SSP_DEBUG_CMD_OE(v) BM_SSP_DEBUG_CMD_OE
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#define BF_SSP_DEBUG_CMD_OE_V(e) BF_SSP_DEBUG_CMD_OE(BV_SSP_DEBUG_CMD_OE__##e)
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#define BFM_SSP_DEBUG_CMD_OE_V(v) BM_SSP_DEBUG_CMD_OE
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#define BP_SSP_DEBUG_DMA_SM 16
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#define BM_SSP_DEBUG_DMA_SM 0x70000
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#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0
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#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1
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#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2
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#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3
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#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4
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#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5
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#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6
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#define BF_SSP_DEBUG_DMA_SM(v) (((v) & 0x7) << 16)
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#define BFM_SSP_DEBUG_DMA_SM(v) BM_SSP_DEBUG_DMA_SM
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#define BF_SSP_DEBUG_DMA_SM_V(e) BF_SSP_DEBUG_DMA_SM(BV_SSP_DEBUG_DMA_SM__##e)
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#define BFM_SSP_DEBUG_DMA_SM_V(v) BM_SSP_DEBUG_DMA_SM
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#define BP_SSP_DEBUG_MMC_SM 12
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#define BM_SSP_DEBUG_MMC_SM 0xf000
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#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0
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#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1
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#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2
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#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3
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#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4
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#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5
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#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6
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#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7
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#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8
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#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9
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#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xa
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#define BF_SSP_DEBUG_MMC_SM(v) (((v) & 0xf) << 12)
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#define BFM_SSP_DEBUG_MMC_SM(v) BM_SSP_DEBUG_MMC_SM
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#define BF_SSP_DEBUG_MMC_SM_V(e) BF_SSP_DEBUG_MMC_SM(BV_SSP_DEBUG_MMC_SM__##e)
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#define BFM_SSP_DEBUG_MMC_SM_V(v) BM_SSP_DEBUG_MMC_SM
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#define BP_SSP_DEBUG_CMD_SM 10
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#define BM_SSP_DEBUG_CMD_SM 0xc00
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#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0
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#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1
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#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2
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#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3
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#define BF_SSP_DEBUG_CMD_SM(v) (((v) & 0x3) << 10)
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#define BFM_SSP_DEBUG_CMD_SM(v) BM_SSP_DEBUG_CMD_SM
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#define BF_SSP_DEBUG_CMD_SM_V(e) BF_SSP_DEBUG_CMD_SM(BV_SSP_DEBUG_CMD_SM__##e)
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#define BFM_SSP_DEBUG_CMD_SM_V(v) BM_SSP_DEBUG_CMD_SM
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#define BP_SSP_DEBUG_SSP_CMD 9
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#define BM_SSP_DEBUG_SSP_CMD 0x200
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#define BF_SSP_DEBUG_SSP_CMD(v) (((v) & 0x1) << 9)
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#define BFM_SSP_DEBUG_SSP_CMD(v) BM_SSP_DEBUG_SSP_CMD
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#define BF_SSP_DEBUG_SSP_CMD_V(e) BF_SSP_DEBUG_SSP_CMD(BV_SSP_DEBUG_SSP_CMD__##e)
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#define BFM_SSP_DEBUG_SSP_CMD_V(v) BM_SSP_DEBUG_SSP_CMD
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#define BP_SSP_DEBUG_SSP_RESP 8
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#define BM_SSP_DEBUG_SSP_RESP 0x100
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#define BF_SSP_DEBUG_SSP_RESP(v) (((v) & 0x1) << 8)
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#define BFM_SSP_DEBUG_SSP_RESP(v) BM_SSP_DEBUG_SSP_RESP
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#define BF_SSP_DEBUG_SSP_RESP_V(e) BF_SSP_DEBUG_SSP_RESP(BV_SSP_DEBUG_SSP_RESP__##e)
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#define BFM_SSP_DEBUG_SSP_RESP_V(v) BM_SSP_DEBUG_SSP_RESP
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#define BP_SSP_DEBUG_SSP_RXD 0
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#define BM_SSP_DEBUG_SSP_RXD 0xff
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#define BF_SSP_DEBUG_SSP_RXD(v) (((v) & 0xff) << 0)
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#define BFM_SSP_DEBUG_SSP_RXD(v) BM_SSP_DEBUG_SSP_RXD
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#define BF_SSP_DEBUG_SSP_RXD_V(e) BF_SSP_DEBUG_SSP_RXD(BV_SSP_DEBUG_SSP_RXD__##e)
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#define BFM_SSP_DEBUG_SSP_RXD_V(v) BM_SSP_DEBUG_SSP_RXD
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#define HW_SSP_VERSION(_n1) HW(SSP_VERSION(_n1))
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#define HWA_SSP_VERSION(_n1) (((_n1) == 1 ? 0x80010000 : 0x80034000) + 0x110)
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#define HWT_SSP_VERSION(_n1) HWIO_32_RW
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#define HWN_SSP_VERSION(_n1) SSP_VERSION
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#define HWI_SSP_VERSION(_n1) (_n1)
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#define BP_SSP_VERSION_MAJOR 24
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#define BM_SSP_VERSION_MAJOR 0xff000000
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#define BF_SSP_VERSION_MAJOR(v) (((v) & 0xff) << 24)
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#define BFM_SSP_VERSION_MAJOR(v) BM_SSP_VERSION_MAJOR
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#define BF_SSP_VERSION_MAJOR_V(e) BF_SSP_VERSION_MAJOR(BV_SSP_VERSION_MAJOR__##e)
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#define BFM_SSP_VERSION_MAJOR_V(v) BM_SSP_VERSION_MAJOR
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#define BP_SSP_VERSION_MINOR 16
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#define BM_SSP_VERSION_MINOR 0xff0000
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#define BF_SSP_VERSION_MINOR(v) (((v) & 0xff) << 16)
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#define BFM_SSP_VERSION_MINOR(v) BM_SSP_VERSION_MINOR
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#define BF_SSP_VERSION_MINOR_V(e) BF_SSP_VERSION_MINOR(BV_SSP_VERSION_MINOR__##e)
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#define BFM_SSP_VERSION_MINOR_V(v) BM_SSP_VERSION_MINOR
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#define BP_SSP_VERSION_STEP 0
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#define BM_SSP_VERSION_STEP 0xffff
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#define BF_SSP_VERSION_STEP(v) (((v) & 0xffff) << 0)
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#define BFM_SSP_VERSION_STEP(v) BM_SSP_VERSION_STEP
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#define BF_SSP_VERSION_STEP_V(e) BF_SSP_VERSION_STEP(BV_SSP_VERSION_STEP__##e)
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#define BFM_SSP_VERSION_STEP_V(v) BM_SSP_VERSION_STEP
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#endif /* __HEADERGEN_STMP3700_SSP_H__*/
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