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9e2c85e076
This is part of the preparation to add support for iPod Nano 3G and Nano 4G. There are some optimisations left, like merging similar blocks of registers that share the same layout, but the base address have changed between SoC generations. Change-Id: I4f06727b4061977141b65d39ae19591bd5b29680
137 lines
3.2 KiB
C
137 lines
3.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <inttypes.h>
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#include "config.h"
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#include "usb.h"
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#include "usb_drv.h"
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#ifdef HAVE_USBSTACK
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#include "usb_core.h"
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#endif
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#include "s5l87xx.h"
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#include "clocking-s5l8702.h"
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#include "usb-designware.h"
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const struct usb_dw_config usb_dw_config =
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{
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.phytype = DWC_PHYTYPE_UTMI_16,
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/* Available FIFO memory: 0x820 words */
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.rx_fifosz = 0x360,
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.nptx_fifosz = 0x40, /* 1 dedicated FIFO for IN0 */
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.ptx_fifosz = 0x180, /* 3 dedicated FIFOs for IN1,IN3,IN5 */
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#ifdef USB_DW_ARCH_SLAVE
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.disable_double_buffering = false,
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#else
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.ahb_burst_len = HBSTLEN_INCR8,
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.ahb_threshold = 8,
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#endif
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};
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void usb_dw_target_enable_clocks()
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{
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clockgate_enable(CLOCKGATE_USBOTG, true);
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clockgate_enable(CLOCKGATE_USBPHY, true);
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OPHYPWR = 0; /* PHY: Power up */
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udelay(10);
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OPHYUNK1 = 1;
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OPHYUNK2 = 0xe3f;
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ORSTCON = 1; /* PHY: Assert Software Reset */
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udelay(10);
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ORSTCON = 0; /* PHY: Deassert Software Reset */
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udelay(10);
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OPHYUNK3 = 0x600;
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OPHYCLK = USB_DW_CLOCK;
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udelay(400);
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}
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void usb_dw_target_disable_clocks()
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{
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OPHYPWR = 0xf; /* PHY: Power down */
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udelay(10);
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ORSTCON = 7; /* PHY: Assert Software Reset */
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udelay(10);
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clockgate_enable(CLOCKGATE_USBOTG, false);
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clockgate_enable(CLOCKGATE_USBPHY, false);
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}
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void usb_dw_target_enable_irq()
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{
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VICINTENABLE(IRQ_USB_FUNC >> 5) = 1 << (IRQ_USB_FUNC & 0x1f);
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}
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void usb_dw_target_disable_irq()
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{
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VICINTENCLEAR(IRQ_USB_FUNC >> 5) = 1 << (IRQ_USB_FUNC & 0x1f);
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}
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void usb_dw_target_clear_irq()
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{
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}
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/* RB API */
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static int usb_status = USB_EXTRACTED;
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void usb_enable(bool on)
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{
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#ifdef HAVE_USBSTACK
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if (on) usb_core_init();
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else usb_core_exit();
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#else
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(void)on;
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#endif
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}
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int usb_detect(void)
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{
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return usb_status;
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}
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void usb_insert_int(void)
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{
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usb_status = USB_INSERTED;
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#ifdef USB_STATUS_BY_EVENT
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usb_status_event(USB_INSERTED);
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#endif
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}
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void usb_remove_int(void)
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{
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usb_status = USB_EXTRACTED;
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#ifdef USB_STATUS_BY_EVENT
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usb_status_event(USB_EXTRACTED);
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#endif
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}
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void usb_init_device(void)
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{
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/* Power up the core clocks to allow writing
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to some registers needed to power it down */
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usb_dw_target_disable_irq();
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usb_dw_target_enable_clocks();
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usb_drv_exit();
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}
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