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9e2c85e076
This is part of the preparation to add support for iPod Nano 3G and Nano 4G. There are some optimisations left, like merging similar blocks of registers that share the same layout, but the base address have changed between SoC generations. Change-Id: I4f06727b4061977141b65d39ae19591bd5b29680
351 lines
9.9 KiB
C
351 lines
9.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id:
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*
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* Copyright (C) 2015 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "config.h"
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#include "system.h" /* udelay() */
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#include "s5l87xx.h"
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#include "clocking-s5l8702.h"
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/* returns configured frequency (PLLxFreq, when locked) */
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unsigned pll_get_cfg_freq(int pll)
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{
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unsigned pdiv, mdiv, sdiv, f_in;
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uint32_t pllpms;
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pllpms = PLLPMS(pll);
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pdiv = (pllpms >> PLLPMS_PDIV_POS) & PLLPMS_PDIV_MSK;
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if (pdiv == 0) return 0;
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mdiv = (pllpms >> PLLPMS_MDIV_POS) & PLLPMS_MDIV_MSK;
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sdiv = (pllpms >> PLLPMS_SDIV_POS) & PLLPMS_SDIV_MSK;
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/* experimental results sugests that the HW is working this way */
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if (mdiv < 2) mdiv += 256;
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if (GET_PMSMOD(pll) == PMSMOD_DIV)
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{
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f_in = (GET_DMOSC(pll))
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? ((PLLMOD2 & PLLMOD2_ALTOSC_BIT(pll))
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? S5L8702_ALTOSC1_HZ
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: S5L8702_ALTOSC0_HZ)
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: S5L8702_OSC0_HZ;
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return (f_in * mdiv / pdiv) >> sdiv; /* divide */
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}
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else
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{
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/* XXX: overflows for high f_in, safe for 32768 Hz */
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f_in = S5L8702_OSC1_HZ;
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return (f_in * mdiv * pdiv) >> sdiv; /* multiply */
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}
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}
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/* returns PLLxClk */
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unsigned pll_get_out_freq(int pll)
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{
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uint32_t pllmode = PLLMODE;
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if ((pllmode & PLLMODE_PLLOUT_BIT(pll)) == 0)
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return S5L8702_OSC1_HZ; /* slow mode */
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if ((pllmode & PLLMODE_EN_BIT(pll)) == 0)
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return 0;
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return pll_get_cfg_freq(pll);
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}
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/* returns selected oscillator for CG16_SEL_OSC source */
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unsigned soc_get_oscsel_freq(void)
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{
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return (PLLMODE & PLLMODE_OSCSEL_BIT) ? S5L8702_OSC1_HZ
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: S5L8702_OSC0_HZ;
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}
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/* returns output frequency */
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unsigned cg16_get_freq(volatile uint16_t* cg16)
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{
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unsigned sel, freq;
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uint16_t val16 = *cg16;
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if (val16 & CG16_DISABLE_BIT)
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return 0;
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sel = (val16 >> CG16_SEL_POS) & CG16_SEL_MSK;
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if (val16 & CG16_UNKOSC_BIT)
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freq = S5L8702_UNKOSC_HZ;
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else if (sel == CG16_SEL_OSC)
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freq = soc_get_oscsel_freq();
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else
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freq = pll_get_out_freq(--sel);
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freq /= (((val16 >> CG16_DIV1_POS) & CG16_DIV1_MSK) + 1) *
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(((val16 >> CG16_DIV2_POS) & CG16_DIV2_MSK) + 1);
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return freq;
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}
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void soc_set_system_divs(unsigned cdiv, unsigned hdiv, unsigned hprat)
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{
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uint32_t val = 0;
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unsigned pdiv = hdiv * hprat;
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if (cdiv > 1)
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val |= CLKCON1_CDIV_EN_BIT |
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((((cdiv >> 1) - 1) & CLKCON1_CDIV_MSK) << CLKCON1_CDIV_POS);
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if (hdiv > 1)
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val |= CLKCON1_HDIV_EN_BIT |
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((((hdiv >> 1) - 1) & CLKCON1_HDIV_MSK) << CLKCON1_HDIV_POS);
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if (pdiv > 1)
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val |= CLKCON1_PDIV_EN_BIT |
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((((pdiv >> 1) - 1) & CLKCON1_PDIV_MSK) << CLKCON1_PDIV_POS);
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val |= ((hprat - 1) & CLKCON1_HPRAT_MSK) << CLKCON1_HPRAT_POS;
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CLKCON1 = val;
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while ((CLKCON1 >> 8) != (val >> 8));
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}
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unsigned soc_get_system_divs(unsigned *cdiv, unsigned *hdiv, unsigned *pdiv)
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{
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uint32_t val = CLKCON1;
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if (cdiv)
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*cdiv = !(val & CLKCON1_CDIV_EN_BIT) ? 1 :
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(((val >> CLKCON1_CDIV_POS) & CLKCON1_CDIV_MSK) + 1) << 1;
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if (hdiv)
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*hdiv = !(val & CLKCON1_HDIV_EN_BIT) ? 1 :
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(((val >> CLKCON1_HDIV_POS) & CLKCON1_HDIV_MSK) + 1) << 1;
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if (pdiv)
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*pdiv = !(val & CLKCON1_PDIV_EN_BIT) ? 1 :
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(((val >> CLKCON1_PDIV_POS) & CLKCON1_PDIV_MSK) + 1) << 1;
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return cg16_get_freq(&CG16_SYS); /* FClk */
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}
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unsigned get_system_freqs(unsigned *cclk, unsigned *hclk, unsigned *pclk)
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{
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unsigned fclk, cdiv, hdiv, pdiv;
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fclk = soc_get_system_divs(&cdiv, &hdiv, &pdiv);
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if (cclk) *cclk = fclk / cdiv;
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if (hclk) *hclk = fclk / hdiv;
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if (pclk) *pclk = fclk / pdiv;
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return fclk;
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}
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void soc_set_hsdiv(int hsdiv)
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{
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SM1_DIV = hsdiv - 1;
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}
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int soc_get_hsdiv(void)
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{
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return (SM1_DIV & 0xf) + 1;
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}
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/* each target/app could define its own clk_modes table */
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struct clocking_mode *clk_modes;
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int cur_level = -1;
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void clocking_init(struct clocking_mode *modes, int level)
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{
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/* at this point, CK16_SYS should be already configured
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and enabled by emCORE/bootloader */
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/* initialize global clocking */
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clk_modes = modes;
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cur_level = level;
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/* start initial level */
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struct clocking_mode *m = clk_modes + cur_level;
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soc_set_hsdiv(m->hsdiv);
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soc_set_system_divs(m->cdiv, m->hdiv, m->hprat);
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}
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void set_clocking_level(int level)
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{
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struct clocking_mode *cur, *next;
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int step = (level < cur_level) ? -1 : 1;
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while (cur_level != level)
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{
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cur = clk_modes + cur_level;
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next = cur + step;
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/* step-up */
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if (next->hsdiv > cur->hsdiv)
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soc_set_hsdiv(next->hsdiv);
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/* step up/down */
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soc_set_system_divs(next->cdiv, next->hdiv, next->hprat);
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/* step-down */
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if (next->hsdiv < cur->hsdiv)
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soc_set_hsdiv(next->hsdiv);
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cur_level += step;
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}
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udelay(50); /* TBC: probably not needed */
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}
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void clockgate_enable(int gate, bool enable)
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{
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int i = (gate >> 5) & 1;
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uint32_t bit = 1 << (gate & 0x1f);
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if (enable) PWRCON(i) &= ~bit;
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else PWRCON(i) |= bit;
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}
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#ifdef BOOTLOADER
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int pll_config(int pll, int op_mode, int p, int m, int s, int lock_time)
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{
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PLLPMS(pll) = ((p & PLLPMS_PDIV_MSK) << PLLPMS_PDIV_POS)
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| ((m & PLLPMS_MDIV_MSK) << PLLPMS_MDIV_POS)
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| ((s & PLLPMS_SDIV_MSK) << PLLPMS_SDIV_POS);
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/* lock_time are PClk ticks */
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PLLCNT(pll) = lock_time & PLLCNT_MSK;
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if (pll < 2)
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{
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if (op_mode == PLLOP_MM) {
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PLLMODE &= ~PLLMODE_PMSMOD_BIT(pll); /* MM */
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return 0;
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}
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PLLMODE |= PLLMODE_PMSMOD_BIT(pll);
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if (op_mode == PLLOP_DM) {
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PLLMOD2 &= ~PLLMOD2_DMOSC_BIT(pll); /* DM */
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return 0;
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}
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PLLMOD2 |= PLLMOD2_DMOSC_BIT(pll);
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}
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else
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{
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if (op_mode == PLLOP_MM)
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return -1; /* PLL2 does not support MM */
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if (op_mode == PLLOP_DM) {
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PLLMODE &= ~PLLMODE_PLL2DMOSC_BIT; /* DM */
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return 0;
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}
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PLLMODE |= PLLMODE_PLL2DMOSC_BIT;
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}
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/* ALTOSCx */
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PLLMOD2 = (PLLMOD2 & ~PLLMOD2_ALTOSC_BIT(pll)) |
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((op_mode == PLLOP_ALT0) ? 0 : PLLMOD2_ALTOSC_BIT(pll));
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return 0;
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}
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int pll_onoff(int pll, bool onoff)
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{
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if (onoff)
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{
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PLLMODE |= PLLMODE_EN_BIT(pll); /* start PLL */
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while (!(PLLLOCK & PLLLOCK_LCK_BIT(pll))); /* locking... */
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PLLMODE |= PLLMODE_PLLOUT_BIT(pll); /* slow mode OFF */
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/* returns DMLCK status, only meaningful for Divisor Mode (DM) */
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return (PLLLOCK & PLLLOCK_DMLCK_BIT(pll)) ? 1 : 0;
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}
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else
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{
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PLLMODE &= ~PLLMODE_PLLOUT_BIT(pll); /* slow mode ON */
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udelay(50); /* TBC: needed when current F_in is 0 Hz */
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PLLMODE &= ~PLLMODE_EN_BIT(pll); /* stop PLL */
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return 0;
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}
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}
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/* configure and enable/disable 16-bit clockgate */
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void cg16_config(volatile uint16_t* cg16,
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bool onoff, int clksel, int div1, int div2)
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{
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uint16_t val16 = ((clksel & CG16_SEL_MSK) << CG16_SEL_POS)
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| (((div1 - 1) & CG16_DIV1_MSK) << CG16_DIV1_POS)
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| (((div2 - 1) & CG16_DIV2_MSK) << CG16_DIV2_POS)
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| (onoff ? 0 : CG16_DISABLE_BIT);
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volatile uint32_t* reg32 = (uint32_t *)((int)cg16 & ~3);
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int shift = ((int)cg16 & 2) << 3;
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*reg32 = (*reg32 & (0xffff0000 >> shift)) | (val16 << shift);
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/*udelay(100);*/ /* probably not needed */
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while (*cg16 != val16);
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}
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/* Configures EClk for USEC_TIMER. DRAM refresh also depends on EClk,
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* this clock should be initialized by the bootloader, so USEC_TIMER
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* is ready to use for RB.
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*/
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void usec_timer_init(void)
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{
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/* select OSC0 for CG16 SEL_OSC */
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PLLMODE &= ~PLLMODE_OSCSEL_BIT;
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/* configure and enable ECLK */
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cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, 1, 1);
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/* unmask timer controller clock gate */
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clockgate_enable(CLOCKGATE_TIMER, true);
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/* configure and start timer E */
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TECON = (4 << 8) | /* TE_CS = ECLK / 1 */
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(1 << 6) | /* select ECLK (12 MHz on Classic) */
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(0 << 4); /* TE_MODE_SEL = interval mode */
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TEPRE = (S5L8702_OSC0_HZ / 1000000) - 1; /* prescaler */
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TEDATA0 = ~0;
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TECMD = (1 << 1) | /* TE_CLR = initialize timer */
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(1 << 0); /* TE_EN = enable */
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}
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#if 0
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/* - This function is mainly to documment how s5l8702 ROMBOOT and iPod
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* Classic diagnostic OF detects primary external clock.
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* - ATM it is unknown if 24 MHz are used on other targets (i.e. Nano 3G),
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* other SoC (ROMBOOT identifies itself as s5l8900/s5l8702), a Classic
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* prototype, or (probably) never used...
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* - This function should be called only at boot time, GPIO3.5 is also
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* used for ATA controller.
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*/
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unsigned soc_get_osc0(void)
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{
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GPIOCMD = 0x30500; /* configure GPIO3.5 as input */
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return (PDAT3 & 0x20) ? 24000000 : 12000000;
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}
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#endif
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#endif /* BOOTLOADER */
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