mirror of
https://github.com/Rockbox/rockbox.git
synced 2026-04-11 16:37:45 -04:00
87f2024631
Unlinking the FMC from the bus clock should make it simpler to do CPU frequency scaling later on. Change-Id: Ia87bbe3dd01ff25ea1520309680017b400471bfe
213 lines
6.1 KiB
C
213 lines
6.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "clock-stm32h7.h"
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#include "lcd-echoplayer.h"
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#include "panic.h"
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#include "regs/stm32h743/flash.h"
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#include "regs/stm32h743/fmc.h"
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#include "regs/stm32h743/pwr.h"
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/syscfg.h"
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#define PLL1Q_FREQ 240000000
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#define PLL3R_FREQ 6000000
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/* Flag to use VOS0 */
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#define STM32H743_USE_VOS0 (CPU_FREQ > 400000000)
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INIT_ATTR static void init_hse(void)
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{
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reg_writef(RCC_CR, HSEON(1));
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while (!reg_readf(RCC_CR, HSERDY));
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}
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INIT_ATTR static void init_pll(void)
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{
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/* For simplicity, PLL parameters are hardcoded */
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_Static_assert(STM32_HSE_FREQ == 24000000,
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"HSE frequency not correct");
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_Static_assert(LCD_DOTCLOCK_FREQ <= PLL3R_FREQ,
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"PLL3R too slow for LCD");
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_Static_assert(PLL1Q_FREQ == 240000000,
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"PLL1Q parameters not correct");
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/*
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* Use HSE/4 input for PLL1
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* Use HSE/12 input for PLL3
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* PLL2 reserved for audio; configured in target PCM code
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*/
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reg_writef(RCC_PLLCKSELR,
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PLLSRC_V(HSE),
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DIVM1(4),
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DIVM2(0),
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DIVM3(12));
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/* Enable PLL1P, PLL1Q, PLL3R */
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reg_writef(RCC_PLLCFGR,
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DIVP1EN(1),
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DIVQ1EN(1),
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DIVR1EN(0),
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DIVP2EN(0),
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DIVQ2EN(0),
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DIVR2EN(0),
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DIVP3EN(0),
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DIVQ3EN(0),
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DIVR3EN(1),
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PLL1RGE_V(4_8MHZ),
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PLL1VCOSEL_V(WIDE),
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PLL1FRACEN(0),
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PLL3RGE_V(1_2MHZ),
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PLL3VCOSEL_V(MEDIUM),
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PLL3FRACEN(0));
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reg_writef(RCC_PLL1DIVR,
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DIVN(80 - 1), /* 6 * 80 = 480 MHz */
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DIVP(1 - 1), /* 480 / 1 = 480 MHz */
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DIVQ(2 - 1), /* 480 / 2 = 240 MHz */
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DIVR(1 - 1));
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reg_writef(RCC_PLL3DIVR,
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DIVN(90 - 1), /* 2 * 90 = 180 MHz */
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DIVP(1 - 1),
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DIVQ(1 - 1),
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DIVR(30 - 1)); /* 180 / 30 = 6 MHz */
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reg_writef(RCC_CR, PLL1ON(1), PLL3ON(1));
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while (!reg_readf(RCC_CR, PLL1RDY));
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while (!reg_readf(RCC_CR, PLL3RDY));
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}
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INIT_ATTR static void init_vos(void)
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{
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reg_writef(PWR_D3CR, VOS_V(VOS1));
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while (!reg_readf(PWR_D3CR, VOSRDY));
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if (STM32H743_USE_VOS0)
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{
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reg_writef(RCC_APB4ENR, SYSCFGEN(1));
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/* Set ODEN bit to enter VOS0 */
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reg_writef(SYSCFG_PWRCFG, ODEN(1));
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while (!reg_readf(PWR_D3CR, VOSRDY));
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reg_writef(RCC_APB4ENR, SYSCFGEN(0));
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}
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}
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INIT_ATTR static void init_system_clock(void)
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{
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/* Enable HCLK /2 divider (CPU is at 480 MHz, HCLK limit is 240 MHz) */
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reg_writef(RCC_D1CFGR, HPRE(8));
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while (reg_readf(RCC_D1CFGR, HPRE) != 8);
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/* Enable ABP /2 dividers (HCLK/2, APB limit is 120 MHz) */
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reg_writef(RCC_D1CFGR, D1PPRE(4));
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reg_writef(RCC_D2CFGR, D2PPRE1(4), D2PPRE2(4));
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reg_writef(RCC_D3CFGR, D3PPRE(4));
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/* Switch to PLL1P system clock source */
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reg_writef(RCC_CFGR, SW_V(PLL1P));
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while (reg_readf(RCC_CFGR, SWS) != BV_RCC_CFGR_SWS_PLL1P);
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/* Reduce flash access latency */
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reg_writef(FLASH_ACR, LATENCY(4), WRHIGHFREQ(2));
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while (reg_readf(FLASH_ACR, LATENCY) != 4);
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}
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INIT_ATTR static void init_lse(void)
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{
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/*
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* Skip if LSE and RTC are already enabled.
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*/
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if (reg_readf(RCC_BDCR, LSERDY) &&
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reg_readf(RCC_BDCR, RTCEN))
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return;
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/*
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* Enable LSE and set it as RTC clock source,
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* then re-enable backup domain write protection.
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*/
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reg_writef(PWR_CR1, DBP(1));
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/* Reset backup domain */
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reg_writef(RCC_BDCR, BDRST(1));
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reg_writef(RCC_BDCR, BDRST(0));
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reg_writef(RCC_BDCR, LSEON(1), LSEDRV(3));
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while (!reg_readf(RCC_BDCR, LSERDY));
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reg_writef(RCC_BDCR, RTCEN(1), RTCSEL_V(LSE));
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reg_writef(PWR_CR1, DBP(0));
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}
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INIT_ATTR static void init_periph_clock(void)
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{
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reg_writef(RCC_D1CCIPR, SDMMCSEL_V(PLL1Q));
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reg_writef(RCC_D2CCIP1R, SAI1SEL_V(PLL2P), SPI45SEL_V(HSE));
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reg_writef(RCC_D2CCIP2R, I2C123SEL_V(HSI));
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/* Enable AXI SRAM in sleep mode to allow DMA'ing out of it */
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reg_writef(RCC_AHB3LPENR, AXISRAMEN(1));
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}
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void echoplayer_clock_init(void)
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{
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init_hse();
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init_pll();
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init_vos();
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init_system_clock();
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init_lse();
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init_periph_clock();
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}
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const struct stm32_clock sdmmc1_ker_clock = {
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.frequency = PLL1Q_FREQ,
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.en_reg = ITA_RCC_AHB3ENR,
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.en_bit = BM_RCC_AHB3ENR_SDMMC1EN,
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.lpen_reg = ITA_RCC_AHB3LPENR,
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.lpen_bit = BM_RCC_AHB3LPENR_SDMMC1EN,
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};
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const struct stm32_clock ltdc_ker_clock = {
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.frequency = PLL3R_FREQ,
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.en_reg = ITA_RCC_APB3ENR,
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.en_bit = BM_RCC_APB3ENR_LTDCEN,
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.lpen_reg = ITA_RCC_APB3LPENR,
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.lpen_bit = BM_RCC_APB3ENR_LTDCEN,
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};
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const struct stm32_clock spi5_ker_clock = {
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.frequency = STM32_HSE_FREQ,
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.en_reg = ITA_RCC_APB2ENR,
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.en_bit = BM_RCC_APB2ENR_SPI5EN,
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.lpen_reg = ITA_RCC_APB2LPENR,
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.lpen_bit = BM_RCC_APB2ENR_SPI5EN,
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};
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const struct stm32_clock i2c1_ker_clock = {
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.frequency = STM32_HSI_FREQ,
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.en_reg = ITA_RCC_APB1LENR,
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.en_bit = BM_RCC_APB1LENR_I2C1EN,
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.lpen_reg = ITA_RCC_APB1LLPENR,
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.lpen_bit = BM_RCC_APB1LENR_I2C1EN,
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};
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