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The Echo R1 is a new open-hardware music player design, based on the STM32H743 microcontroller. Schematics and hardware documentation for it can be found here: - https://github.com/amachronic/echoplayer This is an incomplete port. The bootloader can be loaded using OpenOCD and it can draw to the LCD using SPI. SDRAM is working but hasn't been extensively tested. Change-Id: Ifd2bee15c49868fbc989683d3ca14dce48bf3e18
261 lines
6.6 KiB
C
261 lines
6.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "tick.h"
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#include "gpio-stm32h7.h"
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#include "cortex-m/scb.h"
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#include "cortex-m/systick.h"
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#include "stm32h7/rcc.h"
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#include "stm32h7/pwr.h"
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#include "stm32h7/syscfg.h"
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#include "stm32h7/flash.h"
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/* EXT timer is 1/8th of CPU clock */
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#define SYSTICK_FREQ (CPU_FREQ / 8)
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#define SYSTICK_PER_MS (SYSTICK_FREQ / 1000)
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#define SYSTICK_PER_US (SYSTICK_FREQ / 1000000)
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/* Max delay is limited by kernel tick interval + safety margin */
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#define SYSTICK_DELAY_MAX_US (1000000 / HZ / 2)
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#define SYSTICK_DELAY_MAX_MS (SYSTICK_DELAY_MAX_US / 1000)
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/* Flag to use VOS0 */
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#define STM32H743_USE_VOS0 (CPU_FREQ > 400000000)
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/* Base address of vector table */
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extern char __vectors_arm[];
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static void systick_init(unsigned int interval_in_ms)
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{
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cm_writef(SYSTICK_RVR, VALUE(SYSTICK_PER_MS * interval_in_ms - 1));
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cm_writef(SYSTICK_CVR, VALUE(0));
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cm_writef(SYSTICK_CSR, CLKSOURCE_V(EXT), ENABLE(1));
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}
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static void stm_enable_caches(void)
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{
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__discard_idcache();
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cm_writef(SCB_CCR, IC(1), DC(1));
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arm_dsb();
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arm_isb();
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}
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static void stm_init_hse(void)
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{
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st_writef(RCC_CR, HSEON(1));
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while (!st_readf(RCC_CR, HSERDY));
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}
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static void stm_init_pll(void)
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{
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/* TODO - this should be determined by the target in some way. */
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/* Select HSE/4 input for PLL1 (6 MHz) */
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st_writef(RCC_PLLCKSELR,
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PLLSRC_V(HSE),
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DIVM1(4),
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DIVM2(0),
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DIVM3(0));
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/* Enable PLL1P and PLL1Q */
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st_writef(RCC_PLLCFGR,
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DIVP1EN(1),
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DIVQ1EN(1),
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DIVR1EN(0),
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DIVP2EN(0),
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DIVQ2EN(0),
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DIVR2EN(0),
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DIVP3EN(0),
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DIVQ3EN(0),
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DIVR3EN(0),
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PLL1RGE_V(4_8MHz),
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PLL1VCOSEL_V(WIDE));
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st_writef(RCC_PLL1DIVR,
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DIVN(80 - 1), /* 6 * 80 = 480 MHz */
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DIVP(1 - 1), /* 480 / 1 = 480 MHz */
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DIVQ(8 - 1), /* 480 / 8 = 60 MHz */
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DIVR(1 - 1));
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st_writef(RCC_CR, PLL1ON(1));
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while (!st_readf(RCC_CR, PLL1RDY));
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}
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static void stm_init_vos(void)
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{
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st_writef(PWR_D3CR, VOS_V(VOS1));
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while (!st_readf(PWR_D3CR, VOSRDY));
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if (STM32H743_USE_VOS0)
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{
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st_writef(RCC_APB4ENR, SYSCFGEN(1));
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/* Set ODEN bit to enter VOS0 */
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st_writef(SYSCFG_PWRCFG, ODEN(1));
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while (!st_readf(PWR_D3CR, VOSRDY));
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st_writef(RCC_APB4ENR, SYSCFGEN(0));
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}
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}
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static void stm_init_system_clock(void)
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{
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/* Enable HCLK /2 divider (CPU is at 480 MHz, HCLK limit is 240 MHz) */
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st_writef(RCC_D1CFGR, HPRE(8));
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while (st_readf(RCC_D1CFGR, HPRE) != 8);
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/* Enable ABP /2 dividers (HCLK/2, APB limit is 120 MHz) */
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st_writef(RCC_D1CFGR, D1PPRE(4));
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st_writef(RCC_D2CFGR, D2PPRE1(4), D2PPRE2(4));
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st_writef(RCC_D3CFGR, D3PPRE(4));
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/* Switch to PLL1P system clock source */
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st_writef(RCC_CFGR, SW_V(PLL1P));
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while (st_readf(RCC_CFGR, SWS) != BV_RCC_CFGR_SW__PLL1P);
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/* Reduce flash access latency */
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st_writef(FLASH_ACR, LATENCY(4), WRHIGHFREQ(2));
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while (st_readf(FLASH_ACR, LATENCY) != 4);
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}
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static void stm_init_lse(void)
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{
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/*
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* Skip if LSE and RTC are already enabled.
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*/
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if (st_readf(RCC_BDCR, LSERDY) &&
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st_readf(RCC_BDCR, RTCEN))
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return;
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/*
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* Enable LSE and set it as RTC clock source,
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* then re-enable backup domain write protection.
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*/
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st_writef(PWR_CR1, DBP(1));
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/* Reset backup domain */
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st_writef(RCC_BDCR, BDRST(1));
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st_writef(RCC_BDCR, BDRST(0));
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st_writef(RCC_BDCR, LSEON(1), LSEDRV(3));
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while (!st_readf(RCC_BDCR, LSERDY));
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st_writef(RCC_BDCR, RTCEN(1), RTCSEL_V(LSE));
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st_writef(PWR_CR1, DBP(0));
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}
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void system_init(void)
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{
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/* Ensure IRQs are disabled and set vector table address */
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disable_irq();
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cm_write(SCB_VTOR, (uint32_t)__vectors_arm);
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/* Enable CPU caches */
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stm_enable_caches();
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/* Start up clocks and get running at max CPU frequency */
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stm_init_hse();
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stm_init_pll();
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stm_init_vos();
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stm_init_system_clock();
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/* Start up LSE and RTC if necessary so backup domain works */
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stm_init_lse();
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/* TODO: move this */
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systick_init(1000/HZ);
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/* Call target-specific initialization */
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gpio_init();
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fmc_init();
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}
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void tick_start(unsigned int interval_in_ms)
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{
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(void)interval_in_ms;
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cm_writef(SYSTICK_CSR, TICKINT(1));
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}
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void systick_handler(void)
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{
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call_tick_tasks();
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}
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/*
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* NOTE: This assumes that the CPU cannot be reclocked during an interrupt.
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* If that happens, the systick interval and reload value would be modified
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* to maintain the kernel tick interval and the code here will break.
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*/
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static void __udelay(uint32_t us)
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{
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uint32_t start = cm_readf(SYSTICK_CVR, VALUE);
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uint32_t max = cm_readf(SYSTICK_RVR, VALUE);
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uint32_t delay = us * SYSTICK_PER_US;
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for (;;)
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{
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uint32_t value = cm_readf(SYSTICK_CVR, VALUE);
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uint32_t diff = start - value;
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if (value > start)
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diff += max;
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if (diff >= delay)
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break;
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}
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}
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void udelay(uint32_t us)
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{
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while (us > SYSTICK_DELAY_MAX_US)
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{
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__udelay(SYSTICK_DELAY_MAX_US);
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us -= SYSTICK_DELAY_MAX_US;
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}
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__udelay(us);
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}
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void mdelay(uint32_t ms)
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{
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while (ms > SYSTICK_DELAY_MAX_MS)
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{
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__udelay(SYSTICK_DELAY_MAX_MS * 1000);
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ms -= SYSTICK_DELAY_MAX_MS;
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}
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__udelay(ms * 1000);
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}
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void system_exception_wait(void)
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{
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while (1);
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}
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int system_memory_guard(int newmode)
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{
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/* TODO -- maybe use MPU here to give some basic protection */
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(void)newmode;
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return MEMGUARD_NONE;
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}
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