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The Echo R1 is a new open-hardware music player design, based on the STM32H743 microcontroller. Schematics and hardware documentation for it can be found here: - https://github.com/amachronic/echoplayer This is an incomplete port. The bootloader can be loaded using OpenOCD and it can draw to the LCD using SPI. SDRAM is working but hasn't been extensively tested. Change-Id: Ifd2bee15c49868fbc989683d3ca14dce48bf3e18
302 lines
8.4 KiB
C
302 lines
8.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "spi-stm32h7.h"
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#include "stm32h7/spi.h"
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/*
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* Align the max transfer size to ensure it will always be a multiple
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* of 32 bits. This is necessary because an unaligned TSIZE will cause
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* some data written to the FIFO to be ignored -- this is OK and the
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* intended behavior when it happens at the end of the transfer. But
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* we don't want this to happen when TSER > 0 when we're still in the
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* middle of the transfer, as it will throw away valid data.
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*/
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#define TSIZE_MAX \
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ALIGN_DOWN(st_vreadf(BM_SPI_CR2_TSIZE, SPI_CR2, TSIZE), sizeof(uint32_t))
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static struct stm_spi *spi_map[STM_SPI_COUNT];
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static const uint32_t spi_addr[STM_SPI_COUNT] INITDATA_ATTR = {
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[STM_SPI1] = STA_SPI1,
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[STM_SPI2] = STA_SPI2,
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[STM_SPI3] = STA_SPI3,
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[STM_SPI4] = STA_SPI4,
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[STM_SPI5] = STA_SPI5,
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[STM_SPI6] = STA_SPI6,
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};
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static void stm_spi_set_cs(struct stm_spi *spi, bool enable)
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{
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if (spi->set_cs)
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spi->set_cs(spi, enable);
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st_writelf(spi->regs, SPI_CR1, SSI(1));
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}
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static void stm_spi_enable(struct stm_spi *spi, bool hd_tx, size_t size)
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{
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size_t tsize = size / spi->frame_size;
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size_t tser = 0;
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size_t left = 0;
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if (tsize > TSIZE_MAX)
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{
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tser = tsize - TSIZE_MAX;
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tsize = TSIZE_MAX;
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if (tser > TSIZE_MAX)
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{
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left = tser - TSIZE_MAX;
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tser = TSIZE_MAX;
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}
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}
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/*
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* Save number of bytes left for next TSER load, tracked
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* separately from the overall transfer size because the
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* timing of the SPI_SR.TSERF interrupt isn't clear. We'll
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* decrement this by TSIZE_MAX whenever we load TSER in the
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* middle of a transfer.
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*/
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spi->tser_left = left;
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/* TSIZE must be programmed before setting SPE. */
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st_overwritelf(spi->regs, SPI_CR2, TSIZE(tsize), TSER(tser));
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st_writelf(spi->regs, SPI_CR1, HDDIR(hd_tx), SPE(1));
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}
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static void stm_spi_disable(struct stm_spi *spi)
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{
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st_overwritelf(spi->regs, SPI_IFCR, TSERFC(1), TXTFC(1), EOTC(1));
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st_writelf(spi->regs, SPI_CR1, SPE(0));
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}
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static void stm_spi_start(struct stm_spi *spi)
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{
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st_writelf(spi->regs, SPI_CR1, CSTART(1));
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}
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static uint32_t stm_spi_pack(const void **bufp, size_t *sizep)
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{
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const uint8_t *buf = *bufp;
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uint32_t data = 0;
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if (LIKELY(*sizep >= sizeof(uint32_t)))
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{
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data = load_le32(buf);
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*bufp += sizeof(uint32_t);
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*sizep -= sizeof(uint32_t);
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return data;
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}
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switch (*sizep) {
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case 3: data |= buf[2] << 16; /* fallthrough */
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case 2: data |= buf[1] << 8; /* fallthrough */
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case 1: data |= buf[0]; /* fallthrough */
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}
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*bufp += *sizep;
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*sizep = 0;
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return data;
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}
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static void stm_spi_unpack(void **bufp, size_t *sizep, uint32_t data)
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{
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uint8_t *buf = *bufp;
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if (LIKELY(*sizep >= sizeof(uint32_t)))
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{
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store_le32(buf, data);
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*bufp += sizeof(uint32_t);
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*sizep -= sizeof(uint32_t);
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return;
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}
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switch (*sizep) {
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case 3: buf[2] = (data >> 16) & 0xff; /* fallthrough */
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case 2: buf[1] = (data >> 8) & 0xff; /* fallthrough */
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case 1: buf[0] = data & 0xff; /* fallthrough */
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}
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*bufp += *sizep;
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*sizep = 0;
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}
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void stm_spi_init(struct stm_spi *spi,
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const struct stm_spi_config *config)
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{
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uint32_t ftlevel;
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spi->regs = spi_addr[config->num];
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spi->mode = config->mode;
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spi->set_cs = config->set_cs;
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/* Set FIFO level based on 32-bit packed writes */
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if (config->frame_bits > 16)
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{
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spi->frame_size = 4;
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ftlevel = 1;
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}
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else if (config->frame_bits > 8)
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{
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spi->frame_size = 2;
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ftlevel = 2;
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}
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else
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{
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spi->frame_size = 1;
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ftlevel = 4;
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}
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/*
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* SPI1-3 have a 16-byte FIFO, SPI4-6 have only 8 bytes.
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* So we can double the threshold setting for SPI1-3.
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* (Maximum allowable threshold is 1/2 the FIFO size.)
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*/
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if (config->num <= STM_SPI3)
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ftlevel *= 2;
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/* TODO: allow setting MBR here */
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st_writelf(spi->regs, SPI_CFG1,
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MBR(0),
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CRCEN(0),
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CRCSIZE(7),
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TXDMAEN(0),
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RXDMAEN(0),
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UDRDET(0),
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UDRCFG(0),
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FTHLV(ftlevel - 1),
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DSIZE(config->frame_bits - 1));
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st_writelf(spi->regs, SPI_CFG2,
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AFCNTR(1),
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SSM(config->hw_cs_input ? 0 : 1),
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SSOE(config->hw_cs_output),
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SSIOP(config->hw_cs_polarity),
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CPOL(config->cpol),
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CPHA(config->cpha),
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LSBFIRST(config->send_lsb_first),
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COMM(config->mode),
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SP(config->proto),
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MASTER(1),
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SSOM(0),
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IOSWP(config->swap_mosi_miso),
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MIDI(0),
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MSSI(0));
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spi_map[config->num] = spi;
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}
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int stm_spi_xfer(struct stm_spi *spi, size_t size,
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const void *tx_buf, void *rx_buf)
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{
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bool hd_tx = false;
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size_t size_tx = tx_buf ? size : 0;
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size_t size_rx = rx_buf ? size : 0;
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/* Ignore zero-length transfers. */
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if (size == 0)
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return 0;
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/* Reject nonsensical transfers (no data or less than 1 frame) */
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if (!tx_buf && !rx_buf)
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return -1;
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if (size < spi->frame_size)
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return -1;
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if (spi->mode == STM_SPIMODE_HALF_DUPLEX)
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{
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/* Half duplex mode can't support duplex transfers. */
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if (tx_buf && rx_buf)
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return -1;
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if (tx_buf)
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hd_tx = true;
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}
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stm_spi_set_cs(spi, true);
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stm_spi_enable(spi, hd_tx, size);
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stm_spi_start(spi);
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while (size_tx > 0 || size_rx > 0)
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{
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uint32_t sr = st_readl(spi->regs, SPI_SR);
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/*
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* Handle continuation of large transfers
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*
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* TODO - something is not right with this code
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*/
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if (spi->tser_left > 0 && st_vreadf(sr, SPI_SR, TSERF))
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{
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if (spi->tser_left < TSIZE_MAX)
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{
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st_writelf(spi->regs, SPI_CR2, TSER(spi->tser_left));
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spi->tser_left = 0;
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}
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else
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{
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st_writelf(spi->regs, SPI_CR2, TSER(TSIZE_MAX));
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spi->tser_left -= TSIZE_MAX;
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}
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}
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/* Handle FIFO write */
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if (size_tx > 0 && st_vreadf(sr, SPI_SR, TXP))
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{
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uint32_t data = stm_spi_pack(&tx_buf, &size_tx);
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st_writel(spi->regs, SPI_TXDR32, data);
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}
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/*
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* Handle FIFO read. Since RXP is set only if the FIFO level
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* exceeds the threshold we can't rely on it at the end of a
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* transfer, and must check EOT as well.
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*/
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if (size_rx > 0 &&
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(st_vreadf(sr, SPI_SR, RXP) || st_vreadf(sr, SPI_SR, EOT)))
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{
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uint32_t data = st_readl(spi->regs, SPI_RXDR32);
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stm_spi_unpack(&rx_buf, &size_rx, data);
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}
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}
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/*
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* Errata 2.22.2: Master data transfer stall at system clock much faster than SCK
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* Errata 2.22.6: Truncation of SPI output signals after EOT event
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*
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* For 2.22.2 we need to wait at least 1 SCK cycle before starting the
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* next transaction. For 2.22.6, waiting 1/2 SCK cycle should be enough
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* since the EOT event is raised on a clock edge.
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*
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* TODO: calculate this delay time. doesn't seem to match assumptions above
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*/
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udelay(5);
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stm_spi_disable(spi);
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stm_spi_set_cs(spi, false);
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return 0;
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}
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void spi_irq_handler(void)
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{
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while (1);
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}
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