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The Echo R1 is a new open-hardware music player design, based on the STM32H743 microcontroller. Schematics and hardware documentation for it can be found here: - https://github.com/amachronic/echoplayer This is an incomplete port. The bootloader can be loaded using OpenOCD and it can draw to the LCD using SPI. SDRAM is working but hasn't been extensively tested. Change-Id: Ifd2bee15c49868fbc989683d3ca14dce48bf3e18
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __CPU_STM32H743_H__
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#define __CPU_STM32H743_H__
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#define CACHE_SIZE (16 * 1024)
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#define CACHEALIGN_BITS 5
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#define DCACHE_SIZE CACHE_SIZE
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#define DCACHE_WAYS 0x4
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#define DCACHE_SETS 0x80
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#define DCACHE_LINESIZE (1 << CACHEALIGN_BITS)
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#define STM32_LSI_FREQ 32000
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#define STM32_HSI_FREQ 64000000
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#define STM32_CSI_FREQ 4000000
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#define STM32_HSI48_FREQ 48000000
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#define OTGBASE 0x40080000
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#define USB_NUM_ENDPOINTS 9
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#define STM32_ITCM_BASE 0x00000000
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#define STM32_ITCM_SIZE (64 * 1024)
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#define STM32_DTCM_BASE 0x20000000
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#define STM32_DTCM_SIZE (128 * 1024)
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#define STM32_SRAM_AXI_BASE 0x24000000
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#define STM32_SRAM_AXI_SIZE (512 * 1024)
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#define STM32_SRAM1_BASE 0x30000000
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#define STM32_SRAM1_SIZE (128 * 1024)
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#define STM32_SRAM2_BASE 0x30020000
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#define STM32_SRAM2_SIZE (128 * 1024)
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#define STM32_SRAM3_BASE 0x30040000
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#define STM32_SRAM3_SIZE (128 * 1024)
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#define STM32_SRAM4_BASE 0x38000000
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#define STM32_SRAM4_SIZE (64 * 1024)
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#define STM32_SRAM_BKP_BASE 0x38800000
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#define STM32_SRAM_BKP_SIZE (4 * 1024)
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#define STM32_FLASH_BANK1_BASE 0x08000000
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#define STM32_FLASH_BANK1_SIZE (1024 * 1024)
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#define STM32_FLASH_BANK2_BASE 0x08100000
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#define STM32_FLASH_BANK2_SIZE (1024 * 1024)
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/* FIXME: this changes depending on target settings */
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#define STM32_SDRAM1_BASE 0x70000000
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#endif /* __CPU_STM32H743_H__ */
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