mirror of
https://github.com/Rockbox/rockbox.git
synced 2025-11-20 10:32:42 -05:00
0c7b787398
This is going right in since it's long overdue. If anything is goofed, drop me a line or just tweak it yourself if you know what's wrong. :-) Make HW/SW codec interface more uniform when emulating HW functionality on SWCODEC for functions such as "audiohw_set_pitch". The firmware-to- DSP plumbing is in firmware/drivers/audiohw-swcodec.c. "sound_XXX" APIs are all in sound.c with none in DSP code any longer. Reduce number of settings definitions needed by each codec by providing defaults for common ones like balance, channels and SW tone controls. Remove need for separate SIM code and tables and add virtual codec header for hosted targets. Change-Id: I3f23702bca054fc9bda40f49824ce681bb7f777b
191 lines
5.2 KiB
C
191 lines
5.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Mark Arigo
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _AK4537_H
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#define _AK4537_H
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/* Volume goes from -127.0 ... 0 dB in 0.5 dB increments */
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#define VOLUME_MIN -1270
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#define VOLUME_MAX 0
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AUDIOHW_SETTING(VOLUME, "dB", 0, 1, -128, 0, -25)
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#define AKC_NUM_REGS 0x11
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/* Common register bits */
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/* Power Management 1 */
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#define AK4537_PM1 0x00
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#define PMADL (1 << 0)
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#define PMMICL (1 << 1)
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#define PMIPGL (1 << 2)
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#define PMMO (1 << 3)
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#define PMLO (1 << 4)
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#define PMBPM (1 << 5)
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#define PMBPS (1 << 6)
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#define PMVCM (1 << 7)
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/* Power Management 2 */
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#define AK4537_PM2 0x01
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#define PMDAC (1 << 0)
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#define PMHPR (1 << 1)
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#define PMHPL (1 << 2)
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#define PMSPK (1 << 3)
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#define SPKG (1 << 4)
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#define PMPLL (1 << 5)
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#define PMXTL (1 << 6)
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#define MCLKPD (1 << 7)
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/* Signal Select 1 */
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#define AK4537_SIGSEL1 0x02
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#define MOUT2 (1 << 0)
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#define ALCS (1 << 1)
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#define BPMSP (1 << 2)
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#define BPSSP (1 << 3)
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#define MICM (1 << 4)
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#define DAMO (1 << 5)
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#define PSMO (1 << 6)
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#define MOGN (1 << 7)
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/* Signal Select 2 */
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#define AK4537_SIGSEL2 0x03
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#define HPR (1 << 0)
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#define HPL (1 << 1)
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#define BPMHP (1 << 2)
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#define BPSHP (1 << 3)
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#define MICL (1 << 4)
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#define PSLO (1 << 6)
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#define DAHS (1 << 7)
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/* Mode Control 1 */
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#define AK4537_MODE1 0x04
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#define DIF_MASK (3 << 0)
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#define BICK_MASK (1 << 2)
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#define MCKO_EN (1 << 3)
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#define MCKO_MASK (3 << 4)
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#define MCKI_MASK (3 << 6)
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/* Mode Control 2 */
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#define AK4537_MODE2 0x05
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#define SPPS (1 << 0)
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#define LOOP (1 << 1)
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#define HPM (1 << 2)
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#define FS_MASK (7 << 5)
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/* DAC Control */
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#define AK4537_DAC 0x06
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#define DEM_MASK (3 << 0)
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#define BST_MASK (3 << 2)
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#define DATTC (1 << 4)
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#define SMUTE (1 << 5)
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#define TM_MASK (3 << 6)
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/* MIC Control */
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#define AK4537_MIC 0x07
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#define MGAIN (1 << 0)
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#define MSEL (1 << 1)
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#define MICAD (1 << 2)
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#define MPWRI (1 << 3)
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#define MPWRE (1 << 4)
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#define IPGAC (1 << 5)
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/* Timer Select */
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#define AK4537_TIMER 0x08
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#define LTM_MASK (3 << 0)
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#define WTM_MASK (3 << 2)
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#define ZTM_MASK (3 << 4)
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#define ZTM1 (1 << 5)
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#define ROTM (1 << 6)
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/* ALC Mode Control 1 */
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#define AK4537_ALC1 0x09
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#define LMTH (1 << 0)
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#define RATT (1 << 1)
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#define LMAT_MASK (3 << 2)
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#define ZELM (1 << 4)
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#define ALC1 (1 << 5)
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#define ALC2 (1 << 6)
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/* ALC Mode Control 2 */
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#define AK4537_ALC2 0x0a
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/* Lch Input PGA Control */
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#define AK4537_IPGAL 0x0b
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/* Lch Digital ATT Control */
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#define AK4537_ATTL 0x0c
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/* Rch Digital ATT Control */
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#define AK4537_ATTR 0x0d
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/* Volume Control */
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#define AK4537_VOLUME 0x0e
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#define ATTS_MASK (7 << 4)
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#define ATTRM (1 << 7)
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/* Rch Input PGA Control */
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#define AK4537_IPGAR 0x0f
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/* Power Management 3 */
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#define AK4537_PM3 0x10
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#define PMADR (1 << 0)
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#define PMMICR (1 << 1)
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#define PMIPGR (1 << 2)
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#define INR (1 << 3)
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#define INL (1 << 4)
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/* Sampling frequency (PLL mode) */
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#define AKC_PLL_8000HZ (7 << 5)
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#define AKC_PLL_11025HZ (2 << 5)
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#define AKC_PLL_16000HZ (6 << 5)
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#define AKC_PLL_22050HZ (1 << 5)
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#define AKC_PLL_24000HZ (5 << 5)
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#define AKC_PLL_32000HZ (4 << 5)
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#define AKC_PLL_44100HZ (0 << 5)
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#define AKC_PLL_48000HZ (3 << 5)
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/* MCKI input frequency (PLL mode) */
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#define MCKI_PLL_12288KHZ (0 << 6)
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#define MCKI_PLL_11289KHZ (1 << 6)
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#define MCKI_PLL_12000KHZ (2 << 6)
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/* MCKO frequency (PLL mode, MCKO bit = 1) */
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#define MCKO_PLL_256FS (0 << 4)
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#define MCKO_PLL_128FS (1 << 4)
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#define MCKO_PLL_64FS (2 << 4)
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#define MCKO_PLL_32FS (3 << 4)
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/* BICK frequency */
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#define BICK_64FS (0 << 2)
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#define BICK_32FS (1 << 2)
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/* Audio interface format */
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#define DIF_MSB_LSB (0 << 0)
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#define DIF_MSB_MSB (1 << 0)
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#define DIF_I2S (2 << 0)
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/* Low frequency boost control */
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#define BST_OFF (0 << 2)
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#define BST_MIN (1 << 2)
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#define BST_MID (2 << 2)
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#define BST_MAX (3 << 2)
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#endif /* _AK4537_H */
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