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5aa19f3eeb
CPU frequency scaling is basically useless without scaling the memory frequency. On the i.MX233, the EMI (external memory interface) and DRAM blocks are responsable for the DDR settings. This commits implements emi frequency scaling. Only some settings are implemented and the timings values only apply to mDDR (extracted from Sigmatel linux port) and have been checked to work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled by default but I expected some battery life savings by boosting higher to 454MHz and unboosting lower to 64MHz. Note that changing the emi frequency is particularly tricky and to avoid writing it entirely in assembly we rely on the compiler to not use the stack except in the prolog and epilog (because it's in dram which is disabled when doing the change) and to put constant pools in iram which should always be true if the compiler isn't completely dumb and since the code itself is put in iram. If this proves to be insufficient, one can always switch the stack to the irq stack since interrupts are disabled during the change. Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
270 lines
8.4 KiB
C
270 lines
8.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "gcc_extensions.h"
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#include "system-target.h"
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#include "cpu.h"
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#include "clkctrl-imx233.h"
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#include "pinctrl-imx233.h"
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#include "timrot-imx233.h"
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#include "dma-imx233.h"
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#include "ssp-imx233.h"
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#include "i2c-imx233.h"
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#include "dcp-imx233.h"
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#include "pwm-imx233.h"
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#include "icoll-imx233.h"
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#include "lradc-imx233.h"
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#include "rtc-imx233.h"
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#include "power-imx233.h"
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#include "emi-imx233.h"
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#include "lcd.h"
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#include "backlight-target.h"
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#include "button.h"
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#include "fmradio_i2c.h"
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void imx233_chip_reset(void)
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{
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HW_CLKCTRL_RESET = HW_CLKCTRL_RESET_CHIP;
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}
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void system_reboot(void)
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{
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_backlight_off();
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disable_irq();
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/* use watchdog to reset */
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imx233_chip_reset();
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while(1);
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}
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void system_exception_wait(void)
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{
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/* make sure lcd and backlight are on */
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lcd_update();
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_backlight_on();
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_backlight_set_brightness(DEFAULT_BRIGHTNESS_SETTING);
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/* wait until button release (if a button is pressed) */
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#ifdef HAVE_BUTTON_DATA
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int data;
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while(button_read_device(&data));
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/* then wait until next button press */
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while(!button_read_device(&data));
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#else
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while(button_read_device());
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/* then wait until next button press */
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while(!button_read_device());
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#endif
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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static void set_page_tables(void)
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{
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/* map every memory region to itself */
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map_section(0, 0, 0x1000, CACHE_NONE);
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/* map RAM and enable caching for it */
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map_section(DRAM_ORIG, CACHED_DRAM_ADDR, MEMORYSIZE, CACHE_ALL);
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map_section(DRAM_ORIG, BUFFERED_DRAM_ADDR, MEMORYSIZE, BUFFERED);
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}
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void memory_init(void)
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{
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ttb_init();
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set_page_tables();
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enable_mmu();
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}
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void system_init(void)
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{
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/* NOTE: don't use anything here that might require tick task !
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* It is initialized by kernel_init *after* system_init().
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* The main() will naturally set cpu speed to normal after kernel_init()
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* so don't bother if the cpu is running at 24MHz here. */
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imx233_clkctrl_enable_clock(CLK_PLL, true);
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imx233_rtc_init();
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imx233_icoll_init();
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imx233_pinctrl_init();
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imx233_timrot_init();
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imx233_dma_init();
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imx233_ssp_init();
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imx233_dcp_init();
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imx233_pwm_init();
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imx233_lradc_init();
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imx233_power_init();
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imx233_i2c_init();
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imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_INSTR, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_CPU_DATA, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_TRAFFIC_JAM, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_APBXDMA, true);
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imx233_clkctrl_enable_auto_slow_monitor(AS_APBHDMA, true);
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imx233_clkctrl_set_auto_slow_divisor(AS_DIV_8);
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imx233_clkctrl_enable_auto_slow(true);
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#if !defined(BOOTLOADER) &&(defined(SANSA_FUZEPLUS) || \
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defined(CREATIVE_ZENXFI3) || defined(CREATIVE_ZENXFI2))
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fmradio_i2c_init();
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#endif
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}
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bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
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{
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uint32_t cur = HW_DIGCTL_MICROSECONDS;
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if(ref + us_delay <= ref)
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return !(cur > ref) && !(cur < (ref + us_delay));
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else
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return (cur < ref) || cur >= (ref + us_delay);
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}
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void imx233_reset_block(volatile uint32_t *block_reg)
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{
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/* soft-reset */
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__REG_SET(*block_reg) = __BLOCK_SFTRST;
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/* make sure block is gated off */
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while(!(*block_reg & __BLOCK_CLKGATE));
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/* bring block out of reset */
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__REG_CLR(*block_reg) = __BLOCK_SFTRST;
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while(*block_reg & __BLOCK_SFTRST);
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/* make sure clock is running */
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__REG_CLR(*block_reg) = __BLOCK_CLKGATE;
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while(*block_reg & __BLOCK_CLKGATE);
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}
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void udelay(unsigned us)
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{
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uint32_t ref = HW_DIGCTL_MICROSECONDS;
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while(!imx233_us_elapsed(ref, us));
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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/* don't change the frequency if it is useless (changes are expensive) */
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if(cpu_frequency == frequency)
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return;
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cpu_frequency = frequency;
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/* disable auto-slow (enable back afterwards) */
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bool as = imx233_clkctrl_is_auto_slow_enabled();
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imx233_clkctrl_enable_auto_slow(false);
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/* go back to a known state in safe way:
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* clk_p@24 MHz
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* clk_h@6 MHz
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* WARNING: we must absolutely avoid that clk_h be too low or too high
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* during the change. We first change the clk_p/clk_h ratio to 4 so
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* that it cannot be too high (480/4=120 MHz max) or too low
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* (24/4=6 MHz min). Then we switch clk_p to bypass. We chose a ratio of 4
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* which is greater than all clk_p/clk_h ratios used below so that further
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* changes are safe too */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 4);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, true);
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switch(frequency)
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{
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case IMX233_CPUFREQ_454_MHz:
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/* set VDDD to 1.550 mV (brownout at 1.450 mV) */
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imx233_power_set_regulator(REGULATOR_VDDD, 1550, 1450);
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/* clk_h@clk_p/3 */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 3);
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/* clk_p@ref_cpu/1*18/19 */
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 19);
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 1);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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imx233_emi_set_frequency(IMX233_EMIFREQ_130_MHz);
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/* ref_cpu@480 MHz
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* ref_emi@480 MHz
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* clk_emi@130.91 MHz
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* clk_p@454.74 MHz
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* clk_h@130.91 MHz */
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break;
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case IMX233_CPUFREQ_261_MHz:
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/* set VDDD to 1.275 mV (brownout at 1.175 mV) */
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imx233_power_set_regulator(REGULATOR_VDDD, 1275, 1175);
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/* clk_h@clk_p/2 */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 2);
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/* clk_p@ref_cpu/1*18/33 */
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 33);
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 1);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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imx233_emi_set_frequency(IMX233_EMIFREQ_130_MHz);
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/* ref_cpu@480 MHz
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* ref_emi@480 MHz
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* clk_emi@130.91 MHz
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* clk_p@261.82 MHz
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* clk_h@130.91 MHz */
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break;
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case IMX233_CPUFREQ_64_MHz:
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/* set VDDD to 1.050 mV (brownout at 0.975 mV) */
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imx233_power_set_regulator(REGULATOR_VDDD, 1050, 975);
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/* clk_h@clk_p */
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imx233_clkctrl_set_clock_divisor(CLK_HBUS, 1);
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/* clk_p@ref_cpu/5*18/27 */
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imx233_clkctrl_set_fractional_divisor(CLK_CPU, 27);
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imx233_clkctrl_set_clock_divisor(CLK_CPU, 5);
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imx233_clkctrl_set_bypass_pll(CLK_CPU, false);
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imx233_emi_set_frequency(IMX233_EMIFREQ_64_MHz);
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/* ref_cpu@480 MHz
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* ref_emi@480 MHz
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* clk_emi@64 MHz
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* clk_p@64 MHz
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* clk_h@64 MHz */
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default:
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break;
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}
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/* enable auto slow again */
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imx233_clkctrl_enable_auto_slow(as);
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}
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#endif
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void imx233_enable_usb_controller(bool enable)
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{
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if(enable)
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__REG_CLR(HW_DIGCTL_CTRL) = HW_DIGCTL_CTRL__USB_CLKGATE;
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else
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__REG_SET(HW_DIGCTL_CTRL) = HW_DIGCTL_CTRL__USB_CLKGATE;
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}
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void imx233_enable_usb_phy(bool enable)
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{
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if(enable)
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{
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__REG_CLR(HW_USBPHY_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST;
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__REG_CLR(HW_USBPHY_PWD) = HW_USBPHY_PWD__ALL;
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}
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else
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{
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__REG_SET(HW_USBPHY_PWD) = HW_USBPHY_PWD__ALL;
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__REG_SET(HW_USBPHY_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST;
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}
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}
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