Solomon Peachy 08c4b708ae jz4760: Move 11/22/44/88KHz back onto the PLL ... PLL1 clock for those frequencies has been dropped from 508 to 169.5 MHz, so it's still a respectable reduction. (I'm not sure how/why it ever worked with the XTAL source, but it did, and was off by an audible amount) Change-Id: I614d87e7dfdfe9210702b9c646d3863c06d6780b		2020-08-08 22:29:29 -04:00
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ingenic_jz47xx	jz4760: Move 11/22/44/88KHz back onto the PLL	2020-08-08 22:29:29 -04:00
mmu-mips.c	Add cleaned-up xDuoo X3 support	2018-07-28 10:56:31 -04:00
mmu-mips.h	Add cleaned-up xDuoo X3 support	2018-07-28 10:56:31 -04:00