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99c18f336c
Some 512G Samsung cards (and possibly other cards) seem to have problems with repeated single block read commands and sometimes just time out without ever sending the data. The card response is received OK and reports no errors but no data is received. The problem also occurs if a multiple block read is used to transfer a single block but doesn't seem to occur when more than one block is transferred. Less commonly, timeouts can occur on write commands but it is not clear if that happens only after a timed out read. Adding a delay of a few tens of milliseconds before each read/write single block command appears to prevent this. Change-Id: I5a02b71f59cc02832acaf30e5f900a3ee8804e76
316 lines
10 KiB
C
316 lines
10 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SDMMC_HOST_H__
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#define __SDMMC_HOST_H__
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/*
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* Generic SD/MMC host driver which implements the storage
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* API for targets with SD/MMC based storage. Targets only
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* have to implement a simplified controller interface to
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* process SD/MMC commands, and manage clocks/power.
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*
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* sdmmc_host supports hotswappable storage, but the target
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* is responsible for detecting insertion and removals, and
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* informing sdmmc_host.
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*
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* To enable this driver add the following defines in your
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* target config.h to set the number of SD/MMC controllers
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* on the system:
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*
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* - SDMMC_HOST_NUM_SD_CONTROLLERS
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* - SDMMC_HOST_NUM_MMC_CONTROLLERS
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*
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* You also need to implement `struct sdmmc_controller_ops`
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* for your hardware, and initialize the host drivers for
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* each storage device from the target-specific function
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* `sdmmc_host_target_init()`.
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*/
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#include "storage.h"
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#include "sdmmc.h"
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#include "mutex.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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/* Response length flags */
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#define SDMMC_RESP_NONE 0x00
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#define SDMMC_RESP_SHORT 0x01
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#define SDMMC_RESP_LONG 0x02
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#define SDMMC_RESP_LENGTH(flags) ((flags) & 0x03)
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/* Response requires busy polling */
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#define SDMMC_RESP_BUSY 0x04
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/* Response has no CRC */
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#define SDMMC_RESP_NOCRC 0x08
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/* Data present & direction of data transfer */
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#define SDMMC_DATA_READ 0x10
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#define SDMMC_DATA_WRITE 0x30
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#define SDMMC_DATA_PRESENT(flags) ((flags) & 0x10)
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#define SDMMC_DATA_DIR(flags) ((flags) & 0x30)
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/* Status codes returned by submit_command() callback */
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#define SDMMC_STATUS_OK 0
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#define SDMMC_STATUS_ERROR (-1)
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#define SDMMC_STATUS_TIMEOUT (-2)
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#define SDMMC_STATUS_INVALID_CRC (-3)
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struct sdmmc_host_command
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{
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uint16_t flags;
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uint16_t command;
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uint32_t argument;
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uint16_t nr_blocks;
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uint16_t block_len;
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void *buffer;
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};
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struct sdmmc_host_response
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{
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uint32_t data[4];
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};
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/* Possible bus voltages */
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#define SDMMC_BUS_VOLTAGE_2V7_2V8 (1 << 15)
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#define SDMMC_BUS_VOLTAGE_2V8_2V9 (1 << 16)
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#define SDMMC_BUS_VOLTAGE_2V9_3V0 (1 << 17)
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#define SDMMC_BUS_VOLTAGE_3V0_3V1 (1 << 18)
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#define SDMMC_BUS_VOLTAGE_3V1_3V2 (1 << 19)
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#define SDMMC_BUS_VOLTAGE_3V2_3V3 (1 << 20)
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#define SDMMC_BUS_VOLTAGE_3V3_3V4 (1 << 21)
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#define SDMMC_BUS_VOLTAGE_3V4_3V5 (1 << 22)
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#define SDMMC_BUS_VOLTAGE_3V5_3V6 (1 << 23)
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/* Possible bus widths */
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#define SDMMC_BUS_WIDTH_1BIT (1 << 0)
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#define SDMMC_BUS_WIDTH_4BIT (1 << 1)
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#define SDMMC_BUS_WIDTH_8BIT (1 << 2)
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/* Possible bus clock speeds */
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#define SDMMC_BUS_CLOCK_400KHZ (1 << 0)
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#define SDMMC_BUS_CLOCK_25MHZ (1 << 1)
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#define SDMMC_BUS_CLOCK_50MHZ (1 << 2)
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/**
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* Callbacks for implementing an SD/MMC host controller.
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*
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* Most functions here are called with the sdmmc_host lock
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* held which prevents multiple threads from accessing the
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* same controller.
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*/
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struct sdmmc_controller_ops
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{
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/**
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* \brief Enable/disable power supply of the SD/MMC device
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* \param controller Controller pointer
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* \param enable Whether power should be enabled or not
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*
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* sdmmc_host will try to power cycle the device after
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* non-recoverable errors. Removable devices will also
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* have bus power enabled/disabled when the device is
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* inserted or removed.
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*
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* Even if the target can't physically power cycle the
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* card, a reset of the SDMMC controller is often good
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* enough.
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*
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* Optional. Not implementing this function does not
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* change any behavior of sdmmc_host -- it will still
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* try to recover from errors by reinitializing the
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* SDMMC device.
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*/
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void (*set_power_enabled) (void *controller, bool enable);
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/**
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* \brief Set the bus width (number of active data lines)
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* \param controller Controller pointer
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* \param width One of the SDMMC_BUS_WIDTH constants
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*
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* Optional. If not implemented then the bus width is
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* limited to 1 bit wide.
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*/
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void (*set_bus_width) (void *controller, uint32_t width);
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/**
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* \brief Set the frequency of the clock provided to the SD/MMC device
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* \param controller Controller pointer
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* \param clock One of the SDMMC_BUS_CLOCK constants
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*
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* All controllers must implement this funtion and support
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* at least 400 KHz and 25 MHz rates.
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*/
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void (*set_bus_clock) (void *controller, uint32_t clock);
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/**
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* \brief Submit a command to the controller and wait for the response
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* \param cmd Command descriptor
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* \param resp Response data buffer; may be NULL
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*
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* \retval SDMMC_STATUS_OK if command completed successfully
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* \retval SDMMC_STATUS_TIMEOUT if failed due to command timeout
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* \retval SDMMC_STATUS_INVALID_CRC if failed due to an invalid CRC
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* \retval SDMMC_STATUS_ERROR if failed in any other way
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*
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* Note that if `resp` is NULL, the controller must still use
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* the response format specified in `cmd->flags`; the response
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* data, if any, should be discarded.
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*/
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int (*submit_command) (void *controller,
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const struct sdmmc_host_command *cmd,
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struct sdmmc_host_response *resp);
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/**
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* Abort command processing. Any in-progress call to
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* submit_command() must be made to return as soon as
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* possible with a nonzero status code.
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*
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* If no command is in progress then this function
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* must do nothing.
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*
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* Optional. If not implemented then the controller is
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* responsible for ensuring that submit_command() will
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* eventually return even in case of device removal or
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* a command unexpectedly hanging.
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*
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* May be called without the sdmmc_host lock held.
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*/
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void (*abort_command) (void *controller);
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};
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struct sdmmc_host_config
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{
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/* Storage type: either STORAGE_SD or STORAGE_MMC */
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int type;
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/* Supported voltages, bus widths, and clock speeds */
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uint32_t bus_voltages;
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uint32_t bus_widths;
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uint32_t bus_clocks;
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/* Max number of blocks in a multiblock transfer */
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int max_nr_blocks;
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/* Set to true if the device is removable at runtime */
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bool is_removable;
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};
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struct sdmmc_host
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{
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/* Static configuration */
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struct sdmmc_host_config config;
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/* Physical drive number */
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int drive;
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#ifdef HAVE_HOTSWAP
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/* Medium presence flag */
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volatile int present;
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#endif
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/*
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* Lock which protects most controller operations
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* and mutable sdmmc_host state.
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*/
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struct mutex lock;
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/* Temporary disk cache buffer */
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void *dc_buffer;
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/* Bus & device state flags; must only be accessed with lock held */
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bool enabled : 1;
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bool need_reset : 1;
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bool powered : 1;
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bool initialized : 1;
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bool is_hcs_card : 1;
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bool use_cmd23 : 1;
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bool led_active : 1; /* LED active may be read without lock */
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/*
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* Some 512G Samsung cards (and possibly other cards) seem to
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* have problems with repeated single block read commands and
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* sometimes just time out without ever sending the data. The
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* card response is OK but no data is received.
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*
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* Adding a delay of a few tens of milliseconds before each
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* read/write single block command appears to fix the problem.
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*/
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bool quirk_rdwrsingleblock_delay : 1;
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/* Controller implemented by the target */
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const struct sdmmc_controller_ops *ops;
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void *controller;
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/* Card info probed from card */
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tCardInfo cardinfo;
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};
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/**
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* Called during storage_init() to add SD/MMC host controllers.
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* The target should call sdmmc_host_init() for each controller
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* in the system.
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*/
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void sdmmc_host_target_init(void) INIT_ATTR;
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/**
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* \brief Initialize an SD/MMC host controller
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* \param host Host driver state, allocated by the target
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* \param config Static configuration for host controller
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* \param ops Controller callbacks
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* \param controller Opaque pointer passed to ops callbacks
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*
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* Physical drive numbers will be assigned in the order of
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* initialization, eg. the first host will be drive 0, the
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* second will be drive 1, and so forth.
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*/
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void sdmmc_host_init(struct sdmmc_host *host,
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const struct sdmmc_host_config *config,
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const struct sdmmc_controller_ops *ops,
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void *controller) INIT_ATTR;
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/**
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* \brief Set initial SD/MMC medium presence
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* \param host Host controller
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* \param present True if medium is present
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* \note Only use this function from `sdmmc_host_target_init()` to set
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* the initial medium presence state. Only needs to be called for
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* drives that support removable media; non-removable drives will
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* always be considered inserted.
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*/
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void sdmmc_host_init_medium_present(struct sdmmc_host *host, bool present) INIT_ATTR;
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/**
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* \brief Set SD/MMC medium presence state
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* \param host Host controller
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* \param present True if medium is present
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* \note Do not use this function from `sdmmc_host_target_init()` since
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* it relies on the storage queue being available. You must instead
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* call `sdmmc_host_init_medium_present()` to set the initial state.
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*/
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void sdmmc_host_set_medium_present(struct sdmmc_host *host, bool present);
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/**
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* Returns clock frequency in Hz for an `SDMMC_BUS_CLOCK_*` constant.
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* Returns zero if fed an invalid constant.
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*/
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size_t sdmmc_host_get_bus_freq(uint32_t clock);
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#endif /* __SDMMC_HOST_H__ */
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