mirror of
https://github.com/Rockbox/rockbox.git
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afeefcbec1
No difference in the produced binaries for ipod6g (normal and bootloader) This is a part of the large iPod Nano 3G and iPod Nano 4G support patch. Change-Id: I82943e91ba7e6764428f853f84799f0d54b700a6
139 lines
6.4 KiB
C
139 lines
6.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _DMA_S5l8702_H
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#define _DMA_S5l8702_H
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#include "pl080.h"
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/*
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* s5l8702 PL080 controllers configuration
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*/
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extern struct dmac s5l8702_dmac0;
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extern struct dmac s5l8702_dmac1;
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#define S5L8702_DMAC_COUNT 2 /* N PL080 controllers */
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#define S5L8702_DMAC0_BASE DMA0_BASE
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#define S5L8702_DMAC1_BASE DMA1_BASE
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/* S5L7802 DMAC0 peripherals */
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#define S5L8702_DMAC0_PERI_IIS2_TX 0x0
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#define S5L8702_DMAC0_PERI_IIS2_RX 0x1
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#if CONFIG_CPU == S5L8702
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#define S5L8702_DMAC0_PERI_SPDIF_TX 0x2
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#endif
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#define S5L8702_DMAC0_PERI_LCD_WR 0x3
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#define S5L8702_DMAC0_PERI_SPI0_TX 0x4
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#define S5L8702_DMAC0_PERI_SPI0_RX 0x5
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#define S5L8702_DMAC0_PERI_UART0_TX 0x6
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#define S5L8702_DMAC0_PERI_UART0_RX 0x7
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#define S5L8702_DMAC0_PERI_UART1_TX 0x8
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#define S5L8702_DMAC0_PERI_UART1_RX 0x9
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#define S5L8702_DMAC0_PERI_IIS0_TX 0xA
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#define S5L8702_DMAC0_PERI_IIS0_RX 0xB
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#define S5L8702_DMAC0_PERI_SPI2_TX 0xC
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#define S5L8702_DMAC0_PERI_SPI2_RX 0xD
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#define S5L8702_DMAC0_PERI_SPI1_TX 0xE
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#define S5L8702_DMAC0_PERI_SPI1_RX 0xF
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/* S5L7802 DMAC1 peripherals */
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#define S5L8702_DMAC1_PERI_CEATA_WR 0x0
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#if CONFIG_CPU == S5L8702
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#define S5L8702_DMAC1_PERI_CEATA_RD 0x1
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#endif
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#define S5L8702_DMAC1_PERI_IIS1_TX 0x2
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#define S5L8702_DMAC1_PERI_IIS1_RX 0x3
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#define S5L8702_DMAC1_PERI_IIS2_TX 0x4
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#define S5L8702_DMAC1_PERI_IIS2_RX 0x5
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#if CONFIG_CPU == S5L8702
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#define S5L8702_DMAC1_PERI_SPI1_TX 0x6
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#define S5L8702_DMAC1_PERI_SPI1_RX 0x7
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#endif
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#define S5L8702_DMAC1_PERI_UART2_TX 0x8
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#define S5L8702_DMAC1_PERI_UART2_RX 0x9
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#define S5L8702_DMAC1_PERI_SPI0_TX 0xA
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#define S5L8702_DMAC1_PERI_SPI0_RX 0xB
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#define S5L8702_DMAC1_PERI_UART3_TX 0xC
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#define S5L8702_DMAC1_PERI_UART3_RX 0xD
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#if CONFIG_CPU == S5L8702
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#define S5L8702_DMAC1_PERI_SPI2_TX 0xE
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#define S5L8702_DMAC1_PERI_SPI2_RX 0xF
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#endif
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/* used when src and/or dst peripheral is memory */
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#define S5L8702_DMAC0_PERI_MEM DMAC_PERI_NONE
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#define S5L8702_DMAC1_PERI_MEM DMAC_PERI_NONE
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/* s5l8702 peripheral DMA R/W addesses */
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#define S5L8702_DADDR_PERI_LCD_WR (LCD_BASE + 0x40)
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#if CONFIG_CPU == S5L8702
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#define S5L8702_DADDR_PERI_SPDIF_TX (SPD_BASE + 0x10) /* TBC */
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#endif
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#define S5L8702_DADDR_PERI_UART_TX(i) (UARTC_BASE_ADDR + UARTC_PORT_OFFSET * (i) + 0x20)
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#define S5L8702_DADDR_PERI_UART_RX(i) (UARTC_BASE_ADDR + UARTC_PORT_OFFSET * (i) + 0x24)
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#define S5L8702_DADDR_PERI_UART0_TX S5L8702_DADDR_PERI_UART_TX(0)
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#define S5L8702_DADDR_PERI_UART0_RX S5L8702_DADDR_PERI_UART_RX(0)
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#if CONFIG_CPU == S5L8702
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#define S5L8702_DADDR_PERI_UART1_TX S5L8702_DADDR_PERI_UART_TX(1)
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#define S5L8702_DADDR_PERI_UART1_RX S5L8702_DADDR_PERI_UART_RX(1)
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#define S5L8702_DADDR_PERI_UART2_TX S5L8702_DADDR_PERI_UART_TX(2)
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#define S5L8702_DADDR_PERI_UART2_RX S5L8702_DADDR_PERI_UART_RX(2)
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#define S5L8702_DADDR_PERI_UART3_TX S5L8702_DADDR_PERI_UART_TX(3)
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#define S5L8702_DADDR_PERI_UART3_RX S5L8702_DADDR_PERI_UART_RX(3)
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#elif CONFIG_CPU == S5L8720
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#define S5L8720_DADDR_PERI_UART_TX(i) (UARTC_DMA_BASE_ADDR + UARTC_DMA_PORT_OFFSET * (i - 1) + 0x20)
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#define S5L8720_DADDR_PERI_UART_RX(i) (UARTC_DMA_BASE_ADDR + UARTC_DMA_PORT_OFFSET * (i - 1) + 0x24)
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#define S5L8702_DADDR_PERI_UART1_TX S5L8720_DADDR_PERI_UART_TX(1)
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#define S5L8702_DADDR_PERI_UART1_RX S5L8720_DADDR_PERI_UART_RX(1)
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#define S5L8702_DADDR_PERI_UART2_TX S5L8720_DADDR_PERI_UART_TX(2)
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#define S5L8702_DADDR_PERI_UART2_RX S5L8720_DADDR_PERI_UART_RX(2)
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#define S5L8702_DADDR_PERI_UART3_TX S5L8720_DADDR_PERI_UART_TX(3)
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#define S5L8702_DADDR_PERI_UART3_RX S5L8720_DADDR_PERI_UART_RX(3)
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#endif
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#define S5L8702_DADDR_PERI_IIS_OFFSET(i) ((i) == 2 ? I2S_INTERFACE2_OFFSET : \
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(i) == 1 ? I2S_INTERFACE1_OFFSET : \
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0)
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#define S5L8702_DADDR_PERI_IIS_TX(i) (I2S_BASE + S5L8702_DADDR_PERI_IIS_OFFSET(i) + 0x10)
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#define S5L8702_DADDR_PERI_IIS_RX(i) (I2S_BASE + S5L8702_DADDR_PERI_IIS_OFFSET(i) + 0x38)
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#define S5L8702_DADDR_PERI_IIS0_TX S5L8702_DADDR_PERI_IIS_TX(0)
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#define S5L8702_DADDR_PERI_IIS0_RX S5L8702_DADDR_PERI_IIS_RX(0)
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#define S5L8702_DADDR_PERI_IIS1_TX S5L8702_DADDR_PERI_IIS_TX(1)
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#define S5L8702_DADDR_PERI_IIS1_RX S5L8702_DADDR_PERI_IIS_RX(1)
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#define S5L8702_DADDR_PERI_IIS2_TX S5L8702_DADDR_PERI_IIS_TX(2)
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#define S5L8702_DADDR_PERI_IIS2_RX S5L8702_DADDR_PERI_IIS_RX(2)
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#define S5L8702_DADDR_PERI_CEATA_WR (ATA_UNKNOWN_BASE + 0x80)
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#if CONFIG_CPU == S5L8702
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#define S5L8702_DADDR_PERI_CEATA_RD (ATA_UNKNOWN_BASE + 0x4000 + 0x80)
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#endif
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#define S5L8702_DADDR_PERI_SPI_TX(i) (SPIBASE(i) + 0x10)
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#define S5L8702_DADDR_PERI_SPI_RX(i) (SPIBASE(i) + 0x20)
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#define S5L8702_DADDR_PERI_SPI0_TX S5L8702_DADDR_PERI_SPI_TX(0)
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#define S5L8702_DADDR_PERI_SPI0_RX S5L8702_DADDR_PERI_SPI_RX(0)
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#define S5L8702_DADDR_PERI_SPI1_TX S5L8702_DADDR_PERI_SPI_TX(1)
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#define S5L8702_DADDR_PERI_SPI1_RX S5L8702_DADDR_PERI_SPI_RX(1)
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#define S5L8702_DADDR_PERI_SPI2_TX S5L8702_DADDR_PERI_SPI_TX(2)
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#define S5L8702_DADDR_PERI_SPI2_RX S5L8702_DADDR_PERI_SPI_RX(2)
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/* proto */
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void dma_init(void);
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#endif /* _DMA_S5l8702_H */
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