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361913fdd2
The WM8750 frames its ADC on ADCLRC and its DAC on DACLRC. As the I2S slave both are inputs, and the rk27xx has a single LRCK, which on the YP-CP3 evidently does not reach ADCLRC: with the rk27xx as the master, the recording DMA got exact zeros on most visits to the recording screen and real samples only by chance, sometimes changing partway through a visit. That stays so with the codec PLL no longer glitching the I2S clocks (previous commit); with the codec as the master it does not happen. The codec now drives BCLK and both LRCKs itself, and the rk27xx I2S transmitter and receiver are slaves. The codec's MCLK still comes from the rk27xx codec PLL at 256 fs, so sample rates stay exact. The original firmware runs the codec as master too, but off a fixed 12 MHz in USB mode. RK27XX_I2S_MCLK says the rk27xx makes the codec's MCLK, apart from CODEC_SLAVE, which also makes it the I2S master. The YP-CP3 drops CODEC_SLAVE for RK27XX_I2S_MCLK, and the WM8750 driver sets its master bit as it does for any codec that is not a slave. Tested on a YP-CP3: playback, FM radio, the recording screen's peak meter on every visit, recording from the microphone and from FM. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Change-Id: I0dc93d3b2c45fddf61649702a931d11806e78cbf
475 lines
15 KiB
C
475 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2011 Marcin Bukat
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* Copyright (C) 2011 Andrew Ryabinin
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "kernel.h"
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#include "audio.h"
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#include "string.h"
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#include "panic.h"
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#include "audiohw.h"
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#include "sound.h"
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#include "pcm-internal.h"
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#include "pcm_sink.h"
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static int locked = 0;
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/* HDMA_ISR holds the interrupt masks (bits 8-13) and flags (bits 0-5) of
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* both channels - channel 0 plays, channel 1 records - so each channel
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* updates only its own bits. A flag is cleared by writing 0. */
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#define HDMA_CH0_ISR_BITS ((1<<12) | (1<<10) | (1<<9) | \
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(1<<4) | (1<<2) | (1<<0))
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#define HDMA_CH1_ISR_BITS ((1<<13) | (1<<11) | (1<<8) | \
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(1<<5) | (1<<3) | (1<<1))
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/* running: only the page count down interrupt unmasked, flags clear */
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#define HDMA_CH0_ISR_RUN ((1<<12) | (1<<9))
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#define HDMA_CH1_ISR_RUN ((1<<13) | (1<<8))
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/* stopped: all masked, flags clear */
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#define HDMA_CH0_ISR_STOP ((1<<12) | (1<<10) | (1<<9))
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#define HDMA_CH1_ISR_STOP ((1<<13) | (1<<11) | (1<<8))
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/* count down to zero */
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#define HDMA_CH0_DONE (1<<2)
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#define HDMA_CH1_DONE (1<<3)
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static void hdma_isr_update(unsigned long bits, unsigned long val)
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{
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int old = disable_irq_save();
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HDMA_ISR = (HDMA_ISR & ~bits) | val;
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restore_irq(old);
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}
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/* Mask the DMA interrupt */
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static void sink_lock(void)
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{
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if (++locked == 1)
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{
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int old = disable_irq_save();
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INTC_IMR &= ~IRQ_ARM_HDMA; /* mask HDMA interrupt */
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restore_irq(old);
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}
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}
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/* Unmask the DMA interrupt if enabled */
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static void sink_unlock(void)
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{
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if(--locked == 0)
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{
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int old = disable_irq_save();
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INTC_IMR |= IRQ_ARM_HDMA; /* unmask HDMA interrupt */
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restore_irq(old);
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}
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}
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static void sink_dma_stop(void)
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{
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HDMA_CON0 = 0x00;
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hdma_isr_update(HDMA_CH0_ISR_BITS, HDMA_CH0_ISR_STOP);
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locked = 1;
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}
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static void hdma_i2s_transfer(const void *addr, size_t size)
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{
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SCU_CLKCFG &= ~CLKCFG_HDMA; /* enable HDMA clock */
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commit_discard_dcache_range(addr, size);
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HDMA_ISRC0 = (uint32_t)addr; /* source address */
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HDMA_IDST0 = (uint32_t)&I2S_TXR; /* i2s tx fifo */
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HDMA_ICNT0 = (uint16_t)((size>>2) - 1); /* number of dma transactions
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* of transfer size bytes
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* (zero based)
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*/
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/* mask ch0 accumulation overflow and transfer irqs, unmask its page
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* count down irq, clear its flags */
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hdma_isr_update(HDMA_CH0_ISR_BITS, HDMA_CH0_ISR_RUN);
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HDMA_ISCNT0 = 0x07; /* slice size in transfer size units (zero base) */
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HDMA_IPNCNTD0 = 0x01; /* page count */
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HDMA_CON0 = ((0<<23) | /* page mode */
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(1<<22) | /* slice mode */
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(1<<21) | /* DMA enable */
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(1<<18) | /* generate interrupt */
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(0<<16) | /* on-the-fly is not supported by rk27xx */
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(5<<13) | /* transfer mode inc8 */
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(6<<9) | /* external hdreq from i2s tx */
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(0<<7) | /* increment source address */
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(1<<5) | /* fixed destination address */
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(2<<3) | /* transfer size = 32bits word */
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(0<<1) | /* command of software DMA (not relevant) */
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(1<<0)); /* hardware trigger DMA mode */
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}
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static void sink_dma_start(const void *addr, size_t size)
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{
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/* Stop any DMA in progress */
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sink_dma_stop();
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/* kick in DMA transfer */
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hdma_i2s_transfer(addr, size);
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}
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#define I2S_FORMAT ((1<<16) | /* LRCK/SCLK = 64 */ \
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(4<<8) | /* MCLK/SCLK = 4 */ \
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(1<<4) | /* 16bit samples */ \
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(0<<3) | /* stereo */ \
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(0<<1) | /* I2S IF */ \
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I2S_MASTER)
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#ifdef CODEC_SLAVE
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#define I2S_MASTER (1<<0) /* master mode */
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#else
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#define I2S_MASTER (0<<0) /* slave mode */
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#endif
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static void i2s_init(void)
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{
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#if defined(HAVE_RK27XX_CODEC)
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/* iomux I2S internal */
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SCU_IOMUXA_CON &= ~(1<<19); /* i2s external bit */
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SCU_IOMUXB_CON &= ~((1<<4) | /* i2s_mclk */
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(1<<3) | /* i2s_sdo */
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(1<<2) | /* i2s_sdi */
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(1<<1) | /* i2s_lrck */
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(1<<0)); /* i2s_bck */
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#else
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/* iomux I2S external */
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SCU_IOMUXA_CON |= (1<<19); /* i2s external bit */
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SCU_IOMUXB_CON |= ((1<<4) | /* i2s_mclk */
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(1<<3) | /* i2s_sdo */
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(1<<2) | /* i2s_sdi */
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(1<<1) | /* i2s_lrck */
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(1<<0)); /* i2s_bck */
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#endif
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/* enable i2s clocks */
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SCU_CLKCFG &= ~(CLKCFG_PCLK_I2S | CLKCFG_I2S);
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/* configure I2S module */
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I2S_IER = 0; /* disable all i2s interrupts */
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I2S_TXCTL = I2S_FORMAT;
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#ifdef HAVE_RECORDING
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/* bit 24 as the original firmware of the Samsung YP-CP3 sets it */
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I2S_RXCTL = I2S_FORMAT | (1<<24);
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#endif
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/* the fifo is 16x32bits according to my tests
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* while the docs state 32x32bits
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*/
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I2S_FIFOSTS = (1<<18) | /* Tx trigger level half full */
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(1<<16); /* Rx trigger level half full */
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I2S_OPR = (1<<17) | /* reset Tx */
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(1<<16) | /* reset Rx */
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(0<<6) | /* HDMA Req1 enable */
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(1<<5) | /* HDMA Req2 disable */
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(0<<4) | /* Req1 for Tx fifo */
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(1<<3) | /* Req2 for Rx fifo */
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(0<<2) | /* normal operation */
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#ifdef CODEC_SLAVE
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(1<<1) | /* start Tx (master mode) */
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(0<<0); /* do not start Rx (master mode) */
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/* setting Rx bit to 1 result in choppy audio */
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#else
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(0<<1) | /* not used in slave mode */
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(0<<0); /* not used in slave mode */
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#endif
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}
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#if defined(CODEC_SLAVE) || defined(RK27XX_I2S_MCLK)
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/* When codec is slave, or master off our MCLK (RK27XX_I2S_MCLK), we need
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* to setup i2s MCLK clock using codec pll.
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* The MCLK frequency is 256*codec frequency as i2s setup is:
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* LRCK/SCLK = 64 and MCLK/SCLK = 4 (see i2s_init() for reference)
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*
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* PLL output frequency:
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* Fout = ((Fref / (CLKR+1)) * (CLKF+1)) / (CLKOD+1)
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* Fref = 24 MHz
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*/
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static void set_codec_freq(unsigned int freq)
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{
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static unsigned int cur_freq = HW_NUM_FREQ; /* none yet */
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long timeout;
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/* Reprogramming the PLL glitches MCLK, and with it every clock the
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* codec makes of it: an I2S side started on them can lose its framing.
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* The rate is applied again on every start of recording, mostly
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* unchanged. */
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if (freq == cur_freq)
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return;
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cur_freq = freq;
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/* {CLKR, CLKF, CLKOD, CODECPLL_DIV} */
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static const unsigned int pcm_freq_params[HW_NUM_FREQ][4] =
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{
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HW_HAVE_96_([HW_FREQ_96] = {24, 255, 4, 1},)
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HW_HAVE_48_([HW_FREQ_48] = {24, 127, 4, 1},)
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HW_HAVE_44_([HW_FREQ_44] = {24, 293, 4, 4},)
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HW_HAVE_32_([HW_FREQ_32] = {24, 127, 4, 2},)
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HW_HAVE_24_([HW_FREQ_24] = {24, 127, 4, 3},)
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HW_HAVE_22_([HW_FREQ_22] = {24, 146, 4, 4},)
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HW_HAVE_16_([HW_FREQ_16] = {24, 127, 5, 4},)
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HW_HAVE_12_([HW_FREQ_12] = {24, 127, 4, 7},)
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HW_HAVE_11_([HW_FREQ_11] = {24, 146, 4, 9},)
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HW_HAVE_8_([HW_FREQ_8] = {24, 127, 5, 9},)
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};
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/* select divider output from codec pll */
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SCU_DIVCON1 &= ~((1<<9) | (0xF<<5));
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SCU_DIVCON1 |= (pcm_freq_params[freq][3]<<5);
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/* Codec PLL power up */
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SCU_PLLCON3 &= ~(1<<22);
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SCU_PLLCON3 = (1<<24) | /* Saturation behavior enable */
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(1<<23) | /* Enable fast locking circuit */
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(pcm_freq_params[freq][0]<<16) | /* CLKR factor */
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(pcm_freq_params[freq][1]<<4) | /* CLKF factor */
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(pcm_freq_params[freq][2]<<1) ; /* CLKOD factor */
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/* wait for CODEC PLL lock with 10 ms timeout
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* datasheet states that pll lock should take approx. 0.3 ms; the lock bit
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* may still show the old lock at first
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*/
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udelay(300);
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timeout = current_tick + (HZ/100) + 1;
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while (!(SCU_STATUS & (1<<2)))
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if (TIME_AFTER(current_tick, timeout))
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break;
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/* let the codec's clocks settle before an I2S side starts on them */
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udelay(1000);
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}
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#endif
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static void sink_dma_init(void)
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{
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/* unmask HDMA interrupt in INTC */
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INTC_IMR |= IRQ_ARM_HDMA;
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INTC_IECR |= IRQ_ARM_HDMA;
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/* both channels stopped, with the HDMA clocked for the write */
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SCU_CLKCFG &= ~CLKCFG_HDMA;
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HDMA_ISR = HDMA_CH0_ISR_STOP | HDMA_CH1_ISR_STOP;
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audiohw_preinit();
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i2s_init();
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}
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static void sink_set_freq(uint16_t freq)
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{
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#if defined(CODEC_SLAVE) || defined(RK27XX_I2S_MCLK)
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set_codec_freq(freq);
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#endif
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audiohw_set_frequency(freq);
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}
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#ifdef HAVE_RECORDING
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static void rec_dma_done(void);
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static volatile int rec_locked = 0;
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static volatile bool rec_pending = false;
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#endif
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/* audio DMA ISR called when chunk from callers buffer has been transfered */
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void INT_HDMA(void)
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{
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unsigned long isr = HDMA_ISR;
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if (isr & HDMA_CH0_DONE)
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{
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const void *start;
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size_t size;
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hdma_isr_update(HDMA_CH0_DONE, 0);
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if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
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{
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hdma_i2s_transfer(start, size);
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
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}
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}
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#ifdef HAVE_RECORDING
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if (isr & HDMA_CH1_DONE)
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{
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hdma_isr_update(HDMA_CH1_DONE, 0);
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if (rec_locked)
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{
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rec_pending = true;
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}
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else
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{
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rec_dma_done();
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}
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}
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#endif
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}
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struct pcm_sink builtin_pcm_sink = {
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.caps = {
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.samprs = hw_freq_sampr,
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.num_samprs = HW_NUM_FREQ,
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.default_freq = HW_FREQ_DEFAULT,
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.volume_type = PCM_NATIVE_VOLUME_TYPE,
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},
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.ops = {
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.init = sink_dma_init,
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.postinit = audiohw_postinit,
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.set_freq = sink_set_freq,
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.lock = sink_lock,
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.unlock = sink_unlock,
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.play = sink_dma_start,
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.stop = sink_dma_stop,
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},
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};
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/****************************************************************************
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** Recording DMA transfer
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**/
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#ifdef HAVE_RECORDING
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/* HDMA channel 1 from the I2S Rx FIFO. Playback and recording share the
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* HDMA interrupt, so locking recording cannot mask it; a buffer completed
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* while locked is handed over at unlock instead. */
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/* I2S_OPR while playing only, and while recording too. In master mode the
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* Rx side runs only while recording: started with nothing reading its FIFO
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* it upsets playback. */
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#ifdef CODEC_SLAVE
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#define I2S_OPR_START_TX (1<<1)
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#define I2S_OPR_START_RX (1<<0)
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#else
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#define I2S_OPR_START_TX 0 /* not used in slave mode */
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#define I2S_OPR_START_RX 0
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#endif
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#define I2S_OPR_PLAY ((0<<6) | /* HDMA Req1 enable */ \
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(1<<5) | /* HDMA Req2 disable */ \
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(0<<4) | /* Req1 for Tx fifo */ \
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(1<<3) | /* Req2 for Rx fifo */ \
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I2S_OPR_START_TX)
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#define I2S_OPR_RECORD ((I2S_OPR_PLAY & ~(1<<5)) | I2S_OPR_START_RX)
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static void hdma_i2s_rec_transfer(void *addr, size_t size)
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{
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SCU_CLKCFG &= ~CLKCFG_HDMA; /* enable HDMA clock */
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/* the DMA writes the buffer: no line of it may be written back over
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* the samples later */
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commit_discard_dcache_range(addr, size);
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HDMA_ISRC1 = (uint32_t)&I2S_RXR; /* i2s rx fifo */
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HDMA_IDST1 = (uint32_t)addr; /* destination address */
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HDMA_ICNT1 = (uint16_t)((size>>2) - 1); /* number of dma transactions
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* of transfer size bytes
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* (zero based)
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*/
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hdma_isr_update(HDMA_CH1_ISR_BITS, HDMA_CH1_ISR_RUN);
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HDMA_ISCNT1 = 0x07; /* slice size in transfer size units (zero base) */
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HDMA_IPNCNTD1 = 0x01; /* page count */
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HDMA_CON1 = ((0<<23) | /* page mode */
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(1<<22) | /* slice mode */
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(1<<21) | /* DMA enable */
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(1<<18) | /* generate interrupt */
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(0<<16) | /* on-the-fly is not supported by rk27xx */
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(5<<13) | /* transfer mode inc8 */
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(7<<9) | /* external hdreq from i2s rx */
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(1<<7) | /* fixed source address */
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(0<<5) | /* increment destination address */
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(2<<3) | /* transfer size = 32bits word */
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(0<<1) | /* command of software DMA (not relevant) */
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(1<<0)); /* hardware trigger DMA mode */
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}
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static void rec_dma_done(void)
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{
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void *start;
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size_t size;
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if (pcm_rec_dma_complete_callback(PCM_DMAST_OK, &start, &size))
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{
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hdma_i2s_rec_transfer(start, size);
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pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
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}
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}
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void pcm_rec_lock(void)
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{
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int old = disable_irq_save();
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++rec_locked;
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restore_irq(old);
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}
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void pcm_rec_unlock(void)
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{
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int old = disable_irq_save();
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if (--rec_locked == 0 && rec_pending)
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{
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rec_pending = false;
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rec_dma_done();
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}
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restore_irq(old);
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}
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void pcm_rec_dma_stop(void)
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{
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HDMA_CON1 = 0x00;
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hdma_isr_update(HDMA_CH1_ISR_BITS, HDMA_CH1_ISR_STOP);
|
|
rec_pending = false;
|
|
|
|
I2S_OPR = I2S_OPR_PLAY;
|
|
}
|
|
|
|
void pcm_rec_dma_start(void *addr, size_t size)
|
|
{
|
|
pcm_rec_dma_stop();
|
|
|
|
I2S_OPR = I2S_OPR_PLAY | (1<<16); /* reset Rx */
|
|
I2S_OPR = I2S_OPR_RECORD;
|
|
|
|
hdma_i2s_rec_transfer(addr, size);
|
|
}
|
|
|
|
void pcm_rec_dma_init(void)
|
|
{
|
|
pcm_rec_dma_stop();
|
|
}
|
|
|
|
void pcm_rec_dma_close(void)
|
|
{
|
|
pcm_rec_dma_stop();
|
|
}
|
|
|
|
const void * pcm_rec_dma_get_peak_buffer(void)
|
|
{
|
|
/* where the DMA writes now */
|
|
return (const void *)(HDMA_CDST1 & ~3);
|
|
}
|
|
#endif /* HAVE_RECORDING */
|