Marcin Bukat 69af17695d rk27xx: keep the LCD bus timing at the boosted clock ... The LCD controller's CSn/WEn/RDn strobes count bus clocks, set once for 1-4-1 clocks: a 120 ns write cycle at the 50 MHz bus clock, but 60 ns when the CPU is boosted and the bus runs at 100 MHz. That is too fast for the Samsung YP-CP3's panel: with the CPU boosted it showed stray pixels, and partial updates left tearing behind moving things - the boot logo too, as the firmware boosts before lcd_init(). Double the clocks while boosted, 2-8-2, which keeps the write cycle at 120 ns: set_cpu_frequency() switches them before raising the clock and after lowering it, and lcd init picks them for the clock it runs at - the bootloader stays at crt0's CPUFREQ_MAX. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Change-Id: I482073c16af39c6b1856a0e18d19a747c78975f0		2026-10-02 10:30:58 +02:00
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arm	rk27xx: keep the LCD bus timing at the boosted clock	2026-10-02 10:30:58 +02:00
coldfire	firmware: move iriver flash helper functions into target tree	2026-09-23 13:44:45 -04:00
hosted	Add "rbfs" prefix to native filesystem functions	2026-09-17 16:22:31 -04:00
mips	usb: let controller drivers handle SET_ADDRESS requests	2026-09-26 13:23:01 -04:00