mirror of
https://github.com/Rockbox/rockbox.git
synced 2026-04-11 16:37:45 -04:00
19af7131e2
Allow toggling the system debug state from the debug menu in Rockbox, or by holding a button combo at boot, so that an SWD/JTAG debugger can be attached to normal non-debug builds without too much hassle. Change-Id: Iee47ef916ade2e5ec1094a63c68e48f1b27b0bbb
177 lines
3.3 KiB
Text
177 lines
3.3 KiB
Text
// This file is marked CC0 1.0.
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// To view a copy of this mark, visit https://creativecommons.org/publicdomain/zero/1.0/
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// Register definitions common to ARM Cortex-M series processors
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// Cache controller
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CM_CACHE @ 0xe000ef00 : block {
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ICIALLU @ 0x50 : reg
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ICIMVAU @ 0x58 : reg
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DCIMVAC @ 0x5c : reg
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DCISW @ 0x60 : reg
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DCCMVAU @ 0x64 : reg
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DCCMVAC @ 0x68 : reg
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DCCSW @ 0x6c : reg
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DCCIMVAC @ 0x70 : reg
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DCCISW @ 0x74 : reg
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}
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// Nested vectored interrupt controller
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CM_NVIC @ 0xe000e000 : block {
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ISER @ 0x100 [ 8; 0x4] : reg
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ICER @ 0x180 [ 8; 0x4] : reg
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ISPR @ 0x200 [ 8; 0x4] : reg
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ICPR @ 0x280 [ 8; 0x4] : reg
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IABR @ 0x300 [ 8; 0x4] : reg
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IPR @ 0x400 [60; 0x4] : reg
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STIR @ 0xf00 : reg {
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8 0 INTID
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}
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}
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// System control block
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CM_SCB @ 0xe000ed00 : block {
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ICSR @ 0x04 : reg {
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-- 31 NMIPENDSET
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-- 28 PENDSVSET
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-- 27 PENDSVCLR
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-- 26 PENDSTSET
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-- 25 PENDSTCLR
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-- 23 ISRPREEMPT
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-- 22 ISRPENDING
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20 12 VECTPENDING
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-- 11 RETTOBASE
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08 00 VECTACTIVE
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}
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VTOR @ 0x08 : reg
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AIRCR @ 0x0c : reg {
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31 16 VECTKEY : { 0x05FA = KEY }
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-- 15 ENDIANNESS : { 0 = LITTLE; 1 = BIG }
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10 08 PRIGROUP
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-- 02 SYSRESETREQ
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-- 01 VECTCLRACTIVE
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-- 00 VECTRESET
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}
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SCR @ 0x10 : reg {
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4 SEVONPEND
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2 SLEEPDEEP
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1 SLEEPONEXIT
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}
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CCR @ 0x14 : reg {
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18 BP
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17 IC
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16 DC
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09 STKALIGN
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08 BFHFNMIGN
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04 DIV_0_TRP
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03 UNALIGN_TRP
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01 USERSETMPEND
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00 NONBASETHRDENA
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}
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SHPR1 @ 0x18 : reg {
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23 16 PRI_USAGEFAULT
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15 08 PRI_BUSFAULT
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07 00 PRI_MEMMANAGE
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}
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SHPR2 @ 0x1c : reg {
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31 24 PRI_SVCALL
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}
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SHPR3 @ 0x20 : reg {
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31 24 PRI_SYSTICK
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23 16 PRI_PENDSV
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07 00 PRI_DEBUGMONITOR
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}
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SHCSR @ 0x24 : reg {
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18 USGFAULTENA
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17 BUSFAULTENA
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16 MEMFAULTENA
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15 SVCALLPENDED
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14 BUSFAULTPENDED
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13 MEMFAULTPENDED
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12 USGFAULTPENDED
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11 SYSTICKACT
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10 PENDSVACT
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08 MONITORACT
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07 SVCALLACT
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03 USGFAULTACT
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01 BUSFAULTACT
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00 MEMFAULTACT
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}
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CFSR @ 0x28 : reg {
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// UFSR bits
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25 DIVBYZERO
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24 UNALIGNED
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19 NOCP
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18 INVPC
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17 INVSTATE
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16 UNDEFINSTR
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// BFSR bits
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15 BFARVALID
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13 LSPERR
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12 STKERR
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11 UNSTKERR
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10 IMPRECISERR
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09 PRECISERR
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08 IBUSERR
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// MMSR bits
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07 MMARVALID
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05 MLSPERR
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04 MSTKERR
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03 MUNSTKERR
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01 DACCVIOL
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00 IACCVIOL
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}
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HFSR @ 0x2c : reg {
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31 DEBUGEVT
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30 FORCED
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01 VECTTBL
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}
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MMFAR @ 0x34 : reg
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BFAR @ 0x38 : reg
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CPACR @ 0x88 : reg
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}
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// System timer
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CM_SYSTICK @ 0xe000e000 : block {
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CSR @ 0x10 : reg {
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16 COUNTFLAG
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02 CLKSOURCE : { 0 = EXT; 1 = CPU }
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01 TICKINT
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00 ENABLE
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}
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RVR @ 0x14 : reg {
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23 0 VALUE
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}
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CVR @ 0x18 : reg {
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23 0 VALUE
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}
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CALIB @ 0x1c : reg {
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-- 31 NOREF
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-- 30 SKEW
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23 00 TENMS
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}
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}
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// Debug
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CM_DEBUG @ 0xe000edf0 : block {
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DHCSR @ 0x00 : reg {
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0 C_DEBUGEN
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}
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}
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