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1c96d51717
On ARMv7-M, stm/ldm instructions can't include SP, so we must load and store that separately. This changes the order of registers in the context struct, but it doesn't seem to be accessed anywhere else so this shouldn't cause any problems. Change-Id: Ie1cd23272f23384e030f51f0b76739624fa7332b
105 lines
3.8 KiB
C
105 lines
3.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Thom Johansen
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*
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* Generic ARM threading support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*---------------------------------------------------------------------------
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* Start the thread running and terminate it if it returns
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*---------------------------------------------------------------------------
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*/
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static void __attribute__((naked)) USED_ATTR start_thread(void)
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{
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/* r0 = context */
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asm volatile (
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"ldr sp, [r0, #32] \n" /* Load initial sp */
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"ldr r4, [r0, #40] \n" /* start in r4 since it's non-volatile */
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"mov r1, #0 \n" /* Mark thread as running */
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"str r1, [r0, #40] \n"
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#if NUM_CORES > 1
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"bl commit_discard_idcache \n" /* Invalidate this core's cache. */
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#endif
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"mov lr, pc \n" /* Call thread function */
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"bx r4 \n"
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); /* No clobber list - new thread doesn't care */
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thread_exit();
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#if 0
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asm volatile (".ltorg"); /* Dump constant pool */
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#endif
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}
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/* For startup, place context pointer in r4 slot, start_thread pointer in r5
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* slot, and thread function pointer in context.start. See load_context for
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* what happens when thread is initially going to run. */
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#define THREAD_STARTUP_INIT(core, thread, function) \
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({ (thread)->context.r[0] = (uint32_t)&(thread)->context, \
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(thread)->context.r[1] = (uint32_t)start_thread, \
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(thread)->context.start = (uint32_t)function; })
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/*---------------------------------------------------------------------------
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* Store non-volatile context.
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*---------------------------------------------------------------------------
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*/
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static inline void store_context(void* addr)
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{
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asm volatile(
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#if defined(CPU_ARM_MICRO) && ARCH_VERSION >= 7
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"stmia %0, { r4-r11, lr } \n"
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"str sp, [%0, #36] \n"
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#else
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"stmia %0, { r4-r11, sp, lr } \n"
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#endif
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: : "r" (addr)
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);
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}
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/*---------------------------------------------------------------------------
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* Load non-volatile context.
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*---------------------------------------------------------------------------
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*/
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static inline void load_context(const void* addr)
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{
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asm volatile(
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BEGIN_ARM_ASM_SYNTAX_UNIFIED
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"ldr r0, [%0, #40] \n" /* Load start pointer */
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"cmp r0, #0 \n" /* Check for NULL */
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/* If not already running, jump to start */
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#if ARM_ARCH == 4 && defined(USE_THUMB)
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"ldmiane %0, { r0, r12 } \n"
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"bxne r12 \n"
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#else
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"ldmiane %0, { r0, pc } \n"
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#endif
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#if defined(CPU_ARM_MICRO) && ARCH_VERSION >= 7
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"mov r0, %0 \n"
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"ldmia r0, { r4-r11, lr } \n"
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"ldr sp, [r0, #36] \n"
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#else
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"ldmia %0, { r4-r11, sp, lr } \n" /* Load regs r4 to r14 from context */
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#endif
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END_ARM_ASM_SYNTAX_UNIFIED
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: : "r" (addr) : "r0" /* only! */
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);
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}
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